CIS-77 Home http://www.c-jump.com/CIS77/CIS77syllabus.htm
In Protected mode, when CPU translates addresses, it checks every memory reference to insure it behaves properly.
Effective address is the physical address of the data in memory.
If the effective address (segment base plus offset) is greater than limit field in segment descriptor, the 386 aborts the instruction and generates a protection violation exception.
Programmer can also specify that a segment is read-only, then any write attempt will create the same exception.
If the memory access isn't valid, the CPU generates either a General Protection Fault (GPF).
A GPF indicates that program is trying to access memory that it doesn't have access to.
A page fault indicates that program is trying to access a memory location that doesn't exist.
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Depending on the type of a segment, the descriptor stores other information such as access rights and the like.
In a multitasking operating system, where numerous programs can run simultaneously, programs cannot access the code and data of another process without permission.
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For data segment, B bit controls the size of the stack and stack pointer:
B = 0: SP is used with an upper bound of 0FFFFh (cleared for real mode.)
B = 1: ESP is used with an upper bound of 0FFFFFFFFh (set for protected mode.)
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Pentium uses default segments depending on the purpose of the memory reference.
Instruction fetch - CS register
Stack operations:
in 16-bit mode: SP
in 32-bit mode: ESP.
Accessing data uses DS register.
Actual memory offsets depend on the addressing mode used by the CPU instruction.
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Two views showing x86 logical to virtual to physical memory mapping:
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