<<< The R-S Latch Set Example     Index     The Gated D Latch >>>

5. The R-S Latch Design Requirements

  • The latch must never be supplied S=0 and R=0 at the same time:

    • Cleared S=0 and R=0 at the same time are forbidden inputs.

  • If this happens, subsequent latch value will be undefined.

  • Applying a sequence of logic 0 to the same gate has no effect on the state of the circuit.

  • Only applying a logic 0 to the other gate will cause the latch state change.

  •   R-S latch

<<< The R-S Latch Set Example     Index     The Gated D Latch >>>