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7. The Gated D Latch, Cont.


  • WE input is typically designated as clock input, since it is often controlled by a clock circuit that synchronizes several latch circuits with each other.

  • The output can only change state while clock input is 1.

  • When clock is 0, the S and R inputs have no effect.

  • See also: D NAND latch

  •   Gated D Latch

  • If WE is momentarily asserted, (set to 1), either R or S will be set to 0, depending on the current value of D:

    • if D=1, then S=0, causing the latch to change to 1.

    • if D=0, then R=0, causing the latch to change to 0.

  • Once WE returns to 0, both S and R return to 1, and the value stored in the latch will persist.

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