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INSTRUCTION SET REFERENCE
ANDNPSBit-wise Logical And Not for Single-FP (Continued)
Exceptions
General protection exception if not aligned on 16-byte boundary, regardless of segment.
Numeric Exceptions
None.
Protected Mode Exceptions
#GP(0)
For an illegal memory operand effective address in the CS, DS, ES, FS, or
GS segments.
#SS(0)
For an illegal address in the SS segment.
#PF(fault-code)For a page fault.
#UD
If CR0.EM = 1.
#NM
If TS bit in CR0 is set.
#UD
If CR4.OSFXSR(bit 9) = 0.
#UD
If CPUID.XMM(EDX bit 25) = 0.
Real-Address Mode Exceptions
Interrupt 13
If any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH
#UD
If CR0.EM = 1.
#NM
If TS bit in CR0 is set.
Virtual-8086 Mode Exceptions
Same exceptions as in Real Address Mode.
#PF(fault-code)For a page fault.
#UD
If CR4.OSFXSR(bit 9) = 0.
#UD
If CPUID.XMM(EDX bit 25) = 0.
Comments
The usage of Repeat Prefix (F3H) with ANDNPS is reserved. Different processor implementa-
tions may handle this prefix differently. Usage of this prefix with ANDNPS risks incompatibility
with future processors.
