3-102
INSTRUCTION SET REFERENCE
CMPXCHG8BCompare and Exchange 8 Bytes
Description
This instruction compares the 64-bit value in EDX:EAX with the operand (destination operand).
If the values are equal, the 64-bit value in ECX:EBX is stored in the destination operand. Other-
wise, the value in the destination operand is loaded into EDX:EAX. The destination operand is
an 8-byte memory location. For the EDX:EAX and ECX:EBX register pairs, EDX and ECX
contain the high-order 32 bits and EAX and EBX contain the low-order 32 bits of a 64-bit value.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomi-
cally. To simplify the interface to the processors bus, the destination operand receives a write
cycle without regard to the result of the comparison. The destination operand is written back if
the comparison fails; otherwise, the source operand is written into the destination. (The
processor never produces a locked read without also producing a locked write.)
Intel Architecture Compatibility
This instruction is not supported on Intel processors earlier than the Pentium
®
processors.
Operation
IF (EDX:EAX = DEST)
ZF
<
1
DEST
<
ECX:EBX
ELSE
ZF
<
0
EDX:EAX
<
DEST
Flags Affected
The ZF flag is set if the destination operand and EDX:EAX are equal; otherwise it is cleared.
The CF, PF, AF, SF, and OF flags are unaffected.
Opcode
Instruction
Description
0F C7 /1 m64CMPXCHG8B m64Compare EDX:EAX with m64. If equal, set ZF and load
ECX:EBX into m64. Else, clear ZF and load m64 into
EDX:EAX.
