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INSTRUCTION SET REFERENCE
CPUIDCPU Identification (Continued)
Table 3-8 shows the encoding of the feature flags in the EDX register. A feature flag set to 1
indicates the corresponding feature is supported. Software should identify Intel as the vendor to
properly interpret the feature flags.
Table 3-8. Feature Flags Returned in EDX Register
BitFeature
Description
0FPUFloating-
Point Unit on Chip
Processor contains an FPU and executes the Intel 387 instruction set.
1VMEVirtual-
8086 Mode
Enhancements
Processor supports the following virtual-8086 mode enhancements:
CR4.VME bit enables virtual-8086 mode extensions.
CR4.PVI bit enables protected-mode virtual interrupts.
Expansion of the TSS with the software indirection bitmap.
EFLAGS.VIF bit (virtual interrupt flag).
EFLAGS.VIP bit (virtual interrupt pending flag).
2DEDebugging
Extensions
Processor supports I/O breakpoints, including the CR4.DE bit for enabling
debug extensions and optional trapping of access to the DR4 and DR5
registers.
3PSEPage Size
Extensions
Processor supports 4-Mbyte pages, including the CR4.PSE bit for enabling
page size extensions, the modified bit in page directory entries (PDEs), page
directory entries, and page table entries (PTEs).
4TSCTime
Stamp Counter
Processor supports the RDTSC (read time stamp counter) instruction, including
the CR4.TSD bit that, along with the CPL, controls whether the time stamp
counter can be read.
5MSRModel
Specific Registers
Processor supports the RDMSR (read model-specific register) and WRMSR
(write model-specific register) instructions.
6PAEPhysical
Address
Extension
Processor supports physical addresses greater than 32 bits, the extended
page-table-entry format, an extra level in the page translation tables, and 2-
MByte pages. The CR4.PAE bit enables this feature. The number of address
bits is implementation specific. The Pentium
®
Pro processor supports 36 bits of
addressing when the PAE bit is set.
7MCEMachine
Check Exception
Processor supports the CR4.MCE bit, enabling machine check exceptions.
However, this feature does not define the model-specific implementations of
machine-check error logging, reporting, or processor shutdowns. Machine-
check exception handlers might have to check the processor version to do
model-specific processing of the exception or check for presence of the
machine-check feature.
8CX8CMPXCHG
8B Instruction
Processor supports the CMPXCHG8B (compare and exchange 8 bytes)
instruction.
9APIC
Processor contains an on-chip Advanced Programmable Interrupt Controller
(APIC) and it has been enabled and is available for use.
10Reserved
