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INSTRUCTION SET REFERENCE
FSAVE/FNSAVEStore FPU State
NOTE:
* Refer to Intel Architecture Compatibility below.
Description
These instructions store the current FPU state (operating environment and register stack) at the
specified destination in memory, and then re-initializes the FPU. The FSAVE instruction checks
for and handles pending unmasked floating-point exceptions before storing the FPU state; the
FNSAVE instruction does not.
The FPU operating environment consists of the FPU control word, status word, tag word,
instruction pointer, data pointer, and last opcode. Figures 7-13 through Figures 7-16 in Chapter
7, Floating-Point Unit of the Intel Architecture Software Developers Manual, Volume 1 show
the layout in memory of the stored environment, depending on the operating mode of the
processor (protected or real) and the current operand-size attribute (16-bit or 32-bit). In virtual-
8086 mode, the real mode layouts are used. The contents of the FPU register stack are stored in
the 80 bytes immediately follow the operating environment image.
The saved image reflects the state of the FPU after all floating-point instructions preceding the
FSAVE/FNSAVE instruction in the instruction stream have been executed.
After the FPU state has been saved, the FPU is reset to the same default values it is set to with
the FINIT/FNINIT instructions (refer to FINIT/FNINITInitialize Floating-Point Unit in
this chapter).
The FSAVE/FNSAVE instructions are typically used when the operating system needs to
perform a context switch, an exception handler needs to use the FPU, or an application program
needs to pass a clean FPU to a procedure.
Intel Architecture Compatibility
For Intel math coprocessors and FPUs prior to the Intel Pentium
®
processor, an FWAIT instruc-
tion should be executed before attempting to read from the memory image stored with a prior
FSAVE/FNSAVE instruction. This FWAIT instruction helps insure that the storage operation
has been completed.
On a Pentium
®
III processor, the FSAVE/FNSAVE instructions operate the same as on a
Pentium
®
II processor. They have no effect on the Pentium
®
III processor SIMD floating-point
functional unit or control/status register, i.e., they do not save the SIMD floating-point processor
state.
OpcodeInstruction
Description
9B DD /6FSAVE m94/108byteStore FPU state to m94byte or m108byte after checking for
pending unmasked floating-point exceptions. Then re-
initialize the FPU.
DD /6
FNSAVE
*
m94/108byteStore FPU environment to m94byte or m108byte without
checking for pending unmasked floating-point exceptions.
Then re-initialize the FPU.
