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INSTRUCTION SET REFERENCE
FSTCW/FNSTCWStore Control Word
NOTE:
* Refer to Intel Architecture Compatibility below.
Description
These instructions store the current value of the FPU control word at the specified destination
in memory. The FSTCW instruction checks for and handles pending unmasked floating-point
exceptions before storing the control word; the FNSTCW instruction does not.
Intel Architecture Compatibility
When operating a Pentium
®
or Intel486 processor in MS-DOS compatibility mode, it is
possible (under unusual circumstances) for an FNSTCW instruction to be interrupted prior to
being executed to handle a pending FPU exception. Refer to Section E.2.1.3, No-Wait FPU
Instructions Can Get FPU Interrupt in Window in Appendix E, Guidelines for Writing FPU
Exception Handlers of the Intel Architecture Software Developers Manual, Volume 1, for a
description of these circumstances. An FNSTCW instruction cannot be interrupted in this way
on a Pentium
®
Pro processor.
On a Pentium
®
III processor, the FSTCW/FNSTCW instructions operate the same as on a
Pentium
®
II processor. They have no effect on the Pentium
®
III processor SIMD floating-point
functional unit or control/status register.
Operation
DEST
<
FPUControlWord;
FPU Flags Affected
The C0, C1, C2, and C3 flags are undefined.
Floating-Point Exceptions
None.
Opcode
Instruction
Description
9B D9 /7
FSTCW m2byte
Store FPU control word to m2byte after checking for
pending unmasked floating-point exceptions.
D9 /7
FNSTCW
*
m2byteStore FPU control word to m2byte without checking for
pending unmasked floating-point exceptions.
