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INSTRUCTION SET REFERENCE
FSTENV/FNSTENVStore FPU Environment
NOTE:
* Refer to Intel Architecture Compatibility below.
Description
These instructions save the current FPU operating environment at the memory location specified
with the destination operand, and then masks all floating-point exceptions. The FPU operating
environment consists of the FPU control word, status word, tag word, instruction pointer, data
pointer, and last opcode. Figures 7-13 through Figure 7-16 in Chapter 7, Floating-Point Unit of
the Intel Architecture Software Developers Manual, Volume 1 show the layout in memory of the
stored environment, depending on the operating mode of the processor (protected or real) and
the current operand-size attribute (16-bit or 32-bit). In virtual-8086 mode, the real mode layouts
are used.
The FSTENV instruction checks for and handles any pending unmasked floating-point excep-
tions before storing the FPU environment; the FNSTENV instruction does not.The saved
image reflects the state of the FPU after all floating-point instructions preceding the
FSTENV/FNSTENV instruction in the instruction stream have been executed.
These instructions are often used by exception handlers because they provide access to the FPU
instruction and data pointers. The environment is typically saved in the stack. Masking all
exceptions after saving the environment prevents floating-point exceptions from interrupting the
exception handler.
Intel Architecture Compatibility
When operating a Pentium
®
or Intel486 processor in MS-DOS compatibility mode, it is
possible (under unusual circumstances) for an FNSTENV instruction to be interrupted prior to
being executed to handle a pending FPU exception. Refer to Section E.2.1.3, No-Wait FPU
Instructions Can Get FPU Interrupt in Window in Appendix E, Guidelines for Writing FPU
Exception Handlers of the Intel Architecture Software Developers Manual, Volume 1, for a
description of these circumstances. An FNSTENV instruction cannot be interrupted in this way
on a Pentium
®
Pro processor.
On a Pentium
®
III processor, the FSTENV/FNSTENV instructions operate the same as on a
Pentium
®
II processor. They have no effect on the Pentium
®
III processor SIMD floating-point
functional unit or control/status register.
Opcode
Instruction
Description
9B D9 /6
FSTENV m14/28byteStore FPU environment to m14byte or m28byte after
checking for pending unmasked floating-point
exceptions. Then mask all floating-pointexceptions.
D9 /6
FNSTENV
*
m14/28byteStore FPU environment to m14byte or m28byte without
checking for pending unmasked floating-point
exceptions. Then mask all floating-pointexceptions.
