3-277
INSTRUCTION SET REFERENCE
FXRSTORRestore FP And MMX
State And Streaming SIMD
Extension State (Continued)
Three fields in the floating-point save area contain reserved bits that are not indicated in the
table:
FOP
The lower 11-bits contain the opcode, upper 5-bits are reserved.
IP & DP
32-bit mode: 32-bit IP-offset.
16-bit mode: lower 16 bits are IP-offset and upper 16 bits are reserved.
If the MXCSR state contains an unmasked exception with a corresponding status flag also set,
loading it will not result in a floating-point error condition being asserted. Only the next occur-
rence of this unmasked exception will result in the error condition being asserted.
Some bits of MXCSR (bits 31-16 and bit 6) are defined as reserved and cleared; attempting to
write a non-zero value to these bits will result in a general protection exception.
FXRSTOR does not flush pending x87-FP exceptions, unlike FRSTOR. To check and raise
exceptions when loading a new operating environment, use FWAIT after FXRSTOR.
The Streaming SIMD Extension fields in the save image (XMM0-XMM7 and MXCSR) will not
be loaded into the processor if the CR4.OSFXSR bit is not set. This CR4 bit must be set in order
to enable execution of Streaming SIMD Extension.
Operation
FP and MMX technology state and Streaming SIMD Extension state = m512byte;
Exceptions
#AC
If exception detection is disabled, a general protection exception is
signaled if the address is not aligned on 16-byte boundary. Note that if
#AC is enabled (and CPL is 3), signaling of #AC is not guaranteed and
may vary with implementation. In all implementations where #AC is not
signaled, a general protection fault will instead be signaled. In addition,
the width of the alignment check when #AC is enabled may also vary with
implementation; for instance, for a given implementation, #AC might be
signaled for a 2-byte misalignment, whereas #GP might be signaled for all
other misalignments (4-/8-/16-byte). Invalid opcode exception if instruc-
tion is preceded by a LOCK override prefix. General protection fault if
reserved bits of MXCSR are loaded with non-zero values.
Numeric Exceptions
None.
