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INSTRUCTION SET REFERENCE
INT n/INTO/INT 3Call to Interrupt Procedure (Continued)
When the processor is executing in virtual-8086 mode, the IOPL determines the action of the
INT
n
instruction. If the IOPL is less than 3, the processor generates a general protection excep-
tion (#GP); if the IOPL is 3, the processor executes a protected mode interrupt to privilege level
0. The interrupt gates DPL must be set to three and the target CPL of the interrupt handler proce-
dure must be 0 to execute the protected mode interrupt to privilege level 0.
The interrupt descriptor table register (IDTR) specifies the base linear address and limit of the
IDT. The initial base address value of the IDTR after the processor is powered up or reset is 0.
Operation
The following operational description applies not only to the INT n and INTO instructions, but
also to external interrupts and exceptions.
IF PE=0
THEN
GOTO REAL-ADDRESS-MODE;
ELSE (* PE=1 *)
IF (VM=1 AND IOPL < 3 AND INT n)
THEN
#GP(0);
ELSE (* protected mode or virtual-8086 mode interrupt *)
GOTO PROTECTED-MODE;
FI;
FI;
REAL-ADDRESS-MODE:
IF ((DEST
?
4) + 3) is not within IDT limit THEN #GP; FI;
IF stack not large enough for a 6-byte return information THEN #SS; FI;
Push (EFLAGS[15:0]);
IF
<
0; (* Clear interrupt flag *)
TF
<
0; (* Clear trap flag *)
AC
<
0; (*Clear AC flag*)
Push(CS);
Push(IP);
(* No error codes are pushed *)
CS
<
IDT(Descriptor (vector_number
?
4), selector));
EIP
<
IDT(Descriptor (vector_number
?
4), offset)); (* 16-bit offset AND 0000FFFFH *)
END;
PROTECTED-MODE:
IF ((DEST
?
8) + 7) is not within IDT limits
OR selected IDT descriptor is not an interrupt-, trap-, or task-gate type
THEN #GP((DEST
?
8) + 2 + EXT);
(* EXT is bit 0 in error code *)
FI;
