3-359
INSTRUCTION SET REFERENCE
LGDT/LIDTLoad Global/Interrupt Descriptor Table Register
Description
These instructions load the values in the source operand into the global descriptor table register
(GDTR) or the interrupt descriptor table register (IDTR). The source operand specifies a 6-byte
memory location that contains the base address (a linear address) and the limit (size of table in
bytes) of the global descriptor table (GDT) or the interrupt descriptor table (IDT). If operand-
size attribute is 32 bits, a 16-bit limit (lower two bytes of the 6-byte data operand) and a 32-bit
base address (upper four bytes of the data operand) are loaded into the register. If the
operand-size attribute is 16 bits, a 16-bit limit (lower two bytes) and a 24-bit base address
(third, fourth, and fifth byte) are loaded. Here, the high-order byte of the operand is not used and
the high-order byte of the base address in the GDTR or IDTR is filled with zeroes.
The LGDT and LIDT instructions are used only in operating-system software; they are not used
in application programs. They are the only instructions that directly load a linear address (that
is, not a segment-relative address) and a limit in protected mode. They are commonly executed
in real-address mode to allow processor initialization prior to switching to protected mode.
Refer to SFENCEStore Fence in this chapter for information on storing the contents of the
GDTR and IDTR.
Operation
IF instruction is LIDT
THEN
IF OperandSize = 16
THEN
IDTR(Limit)
<
SRC[0:15];
IDTR(Base)
<
SRC[16:47] AND 00FFFFFFH;
ELSE (* 32-bit Operand Size *)
IDTR(Limit)
<
SRC[0:15];
IDTR(Base)
<
SRC[16:47];
FI;
ELSE (* instruction is LGDT *)
IF OperandSize = 16
THEN
GDTR(Limit)
<
SRC[0:15];
GDTR(Base)
<
SRC[16:47] AND 00FFFFFFH;
ELSE (* 32-bit Operand Size *)
GDTR(Limit)
<
SRC[0:15];
GDTR(Base)
<
SRC[16:47];
FI; FI;
Opcode
Instruction
Description
0F 01 /2
LGDT m16&32
Load m into GDTR
0F 01 /3
LIDT m16&32
Load m into IDTR
