3-365
INSTRUCTION SET REFERENCE
LMSWLoad Machine Status Word
Description
This instruction loads the source operand into the machine status word, bits 0 through 15 of
register CR0. The source operand can be a 16-bit general-purpose register or a memory location.
Only the low-order four bits of the source operand (which contains the PE, MP, EM, and TS
flags) are loaded into CR0. The PG, CD, NW, AM, WP, NE, and ET flags of CR0 are not
affected. The operand-size attribute has no effect on this instruction.
If the PE flag of the source operand (bit 0) is set to 1, the instruction causes the processor to
switch to protected mode. While in protected mode, the LMSW instruction cannot be used clear
the PE flag and force a switch back to real-address mode.
The LMSW instruction is provided for use in operating-system software; it should not be used
in application programs. In protected or virtual-8086 mode, it can only be executed at CPL 0.
This instruction is provided for compatibility with the Intel 286 processor; programs and proce-
dures intended to run on the P6 family, Intel486, and Intel386 processors should use the
MOV (control registers) instruction to load the whole CR0 register. The MOV CR0 instruction
can be used to set and clear the PE flag in CR0, allowing a procedure or program to switch
between protected and real-address modes.
This instruction is a serializing instruction.
Operation
CR0[0:3]
<
SRC[0:3];
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If a memory operand effective address is outside the CS, DS, ES, FS, or
GS segment limit.
If the DS, ES, FS, or GS register is used to access memory and it contains
a null segment selector.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)If a page fault occurs.
Opcode
Instruction
Description
0F 01 /6
LMSW r/m16
Loads r/m16 in machine status word of CR0
