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INSTRUCTION SET REFERENCE
LOCKAssert LOCK# Signal Prefix
Description
This instruction causes the processors LOCK# signal to be asserted during execution of the
accompanying instruction (turns the instruction into an atomic instruction). In a multiprocessor
environment, the LOCK# signal insures that the processor has exclusive use of any shared
memory while the signal is asserted.
Note that in later Intel Architecture processors (such as the Pentium
®
Pro processor), locking
may occur without the LOCK# signal being asserted. Refer to Intel Architecture Compatibility
below.
The LOCK prefix can be prepended only to the following instructions and to those forms of the
instructions that use a memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG,
DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG. An undefined opcode
exception will be generated if the LOCK prefix is used with any other instruction. The XCHG
instruction always asserts the LOCK# signal regardless of the presence or absence of the LOCK
prefix.
The LOCK prefix is typically used with the BTS instruction to perform a read-modify-write
operation on a memory location in shared memory environment.
The integrity of the LOCK prefix is not affected by the alignment of the memory field. Memory
locking is observed for arbitrarily misaligned fields.
Intel Architecture Compatibility
Beginning with the Pentium
®
Pro processor, when the LOCK prefix is prefixed to an instruction
and the memory area being accessed is cached internally in the processor, the LOCK# signal is
generally not asserted. Instead, only the processors cache is locked. Here, the processors cache
coherency mechanism insures that the operation is carried out atomically with regards to
memory. Refer to Section 7.1.4., Effects of a LOCK Operation on Internal Processor Caches in
Chapter 7, Multiple-Processor Management of the Intel Architecture Software Developers
Manual, Volume 3, the for more information on locking of caches.
Operation
AssertLOCK#(DurationOfAccompaningInstruction)
Flags Affected
None.
Opcode
Instruction
Description
F0
LOCK
Asserts LOCK# signal for duration of the accompanying
instruction
