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INSTRUCTION SET REFERENCE
MASKMOVQByte Mask Write
Description
Data is stored from the mm1 register to the location specified by the di/edi register (using DS
segment). The size of the store depends on the address-size attribute. The most significant bit in
each byte of the mask register mm2 is used to selectively write the data (0 = no write, 1 = write)
on a per-byte basis. Behavior with a mask of all zeroes is as follows:
No data will be written to memory. However, transition from FP to MMX technology
state (if necessary) will occur, irrespective of the value of the mask.
For memory references, a zero byte mask does not prevent addressing faults (i.e., #GP,
#SS) from being signaled.
Signaling of page faults (#PG) is implementation-specific.
#UD, #NM, #MF, and #AC faults are signaled irrespective of the value of the mask.
Signaling of breakpoints (code or data) is not guaranteed; different processor implementa-
tions may signal or not signal these breakpoints.
If the destination memory region is mapped as UC or WP, enforcement of associated
semantics for these memory types is not guaranteed (i.e., is reserved) and is implemen-
tation-specific. Dependence on the behavior of a specific implementation in this case is not
recommended, and may lead to future incompatibility.
The Mod field of the ModR/M byte must be 11, or an Invalid Opcode Exception will result.
OpcodeInstruction
Description
0F,F7,/rMASKMOVQ
mm1, mm2
Move 64-bits representing integer data from MM1 register to memory
location specified by the edi register, using the byte mask in MM2
register.
