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INSTRUCTION SET REFERENCE
MOVMove (Continued)
If the destination operand is a segment register (DS, ES, FS, GS, or SS), the source operand must
be a valid segment selector. In protected mode, moving a segment selector into a segment
register automatically causes the segment descriptor information associated with that segment
selector to be loaded into the hidden (shadow) part of the segment register. While loading this
information, the segment selector and segment descriptor information is validated (refer to the
Operation algorithm below). The segment descriptor data is obtained from the GDT or LDT
entry for the specified segment selector.
A null segment selector (values 0000-0003) can be loaded into the DS, ES, FS, and GS registers
without causing a protection exception. However, any subsequent attempt to reference a
segment whose corresponding segment register is loaded with a null value causes a general
protection exception (#GP) and no memory reference occurs.
Loading the SS register with a MOV instruction inhibits all interrupts until after the execution
of the next instruction. This operation allows a stack pointer to be loaded into the ESP register
with the next instruction (MOV ESP, stack-pointer value) before an interrupt occurs
1
. The LSS
instruction offers a more efficient method of loading the SS and ESP registers.
When operating in 32-bit mode and moving data between a segment register and a general-
purpose register, the Intel Architecture 32-bit family of processors do not require the use of the
16-bit operand-size prefix (a byte with the value 66H) with this instruction, but most assemblers
will insert it if the typical form of the instruction is used (for example, MOV DS, AX). The
processor will execute this instruction correctly, but it will usually require an extra clock. With
most assemblers, using the instruction form MOV DS, EAX will avoid this unneeded 66H
prefix. When the processor executes the instruction with a 32-bit general-purpose register, it
assumes that the 16 least-significant bits of the general-purpose register are the destination or
source operand. If the register is a destination operand, the resulting value in the two high-order
bytes of the register is implementation dependent. For the Pentium
®
Pro processor, the two high-
order bytes are filled with zeroes; for earlier 32-bit Intel Architecture processors, the two high
order bytes are undefined.
1.Note that in a sequence of instructions that individually delay interrupts past the following instruction, only
the first instruction in the sequence is guaranteed to delay the interrupt, but subsequent interrupt-delaying
instructions may not delay the interrupt. Thus, in the following instruction sequence:
STI
MOV SS, EAX
MOV ESP, EBP
interrupts may be recognized before MOV ESP, EBP executes, because STI also delays interrupts for
one instruction.
