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INSTRUCTION SET REFERENCE
MOVAPSMove Aligned Four Packed Single-FP (Continued)
Protected Mode Exceptions
#GP(0)
For an illegal memory operand effective address in the CS, DS, ES, FS, or
GS segments.
#SS(0)
For an illegal address in the SS segment.
#PF(fault-code)For a page fault.
#UD
If CR0.EM = 1.
#NM
If TS bit in CR0 is set.
#UD
If CR4.OSFXSR(bit 9) = 0.
#UD
If CPUID.XMM(EDX bit 25) = 0.
Real Address Mode Exceptions
Interrupt 13
If any part of the operand would lie outside of the effective address space
from 0 to 0FFFFH.
#UD
If CR0.EM = 1.
#NM
If TS bit in CR0 is set.
#UD
If CR4.OSFXSR(bit 9) = 0.
#UD
If CPUID.XMM(EDX bit 25) = 0.
Virtual 8086 Mode Exceptions
Same exceptions as in Real Address Mode.
#PF(fault-code) For a page fault.
Comments
MOVAPS should be used when dealing with 16-byte aligned SP FP numbers. If the data is not
known to be aligned, MOVUPS should be used instead of MOVAPS. The usage of this instruc-
tion should be limited to the cases where the aligned restriction is easy to meet. Processors that
support Streaming SIMD Extension will provide optimal aligned performance for the MOVAPS
instruction.
The usage of Repeat Prefix (F3H) with MOVAPS is reserved. Different processor implementa-
tions may handle this prefix differently. Usage of this prefix with MOVAPS risks incompati-
bility with future processors.
