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INSTRUCTION SET REFERENCE
PSRLW/PSRLD/PSRLQ—Packed Shift Right Logical (Continued)
Pre-4.0 Intel C/C++ Compiler intrinsic:
__m64 _m_psrlqi (__m64 m, int count)
Version 4.0 and later Intel C/C++ Compiler intrinsic:
__m64 _mm_srli_si64 (__m64 m, int count)
Shifts the 64-bit value in m right the amount specified by count while shifting in zeroes. For the
best performance, count should be a constant.
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If a memory operand effective address is outside the CS, DS, ES, FS, or
GS segment limit.
#SS(0)
If a memory operand effective address is outside the SS segment limit.
#UD
If EM in CR0 is set.
#NM
If TS in CR0 is set.
#MF
If there is a pending FPU exception.
#PF(fault-code)If a page fault occurs.
#AC(0)
If alignment checking is enabled and an unaligned memory reference is
made while the current privilege level is 3.
Real-Address Mode Exceptions
#GP
If any part of the operand lies outside of the effective address space from
0 to FFFFH.
#UD
If EM in CR0 is set.
#NM
If TS in CR0 is set.
#MF
If there is a pending FPU exception.
