3-600
INSTRUCTION SET REFERENCE
RDMSRRead from Model Specific Register
Description
This instruction loads the contents of a 64-bit model specific register (MSR) specified in the
ECX register into registers EDX:EAX. The EDX register is loaded with the high-order 32 bits
of the MSR and the EAX register is loaded with the low-order 32 bits. If less than 64 bits are
implemented in the MSR being read, the values returned to EDX:EAX in unimplemented bit
locations are undefined.
This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a
general protection exception #GP(0) will be generated. Specifying a reserved or unimplemented
MSR address in ECX will also cause a general protection exception.
The MSRs control functions for testability, execution tracing, performance-monitoring and
machine check errors. Appendix B, Model-Specific Registers, in the Intel Architecture Software
Developers Manual, Volume 3, lists all the MSRs that can be read with this instruction and their
addresses.
The CPUID instruction should be used to determine whether MSRs are supported (EDX[5]=1)
before using this instruction.
Intel Architecture Compatibility
The MSRs and the ability to read them with the RDMSR instruction were introduced into the
Intel Architecture with the Pentium
®
processor. Execution of this instruction by an Intel Archi-
tecture processor earlier than the Pentium
®
processor results in an invalid opcode exception
#UD.
Operation
EDX:EAX
<
MSR[ECX];
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If the current privilege level is not 0.
If the value in ECX specifies a reserved or unimplemented MSR address.
Opcode
Instruction
Description
0F 32
RDMSR
Load MSR specified by ECX into EDX:EAX
