3-602
INSTRUCTION SET REFERENCE
RDPMCRead Performance-Monitoring Counters
Description
This instruction loads the contents of the 40-bit performance-monitoring counter specified in the
ECX register into registers EDX:EAX. The EDX register is loaded with the high-order eight bits
of the counter and the EAX register is loaded with the low-order 32 bits. The Pentium
®
Pro
processor has two performance-monitoring counters (0 and 1), which are specified by placing
0000H or 0001H, respectively, in the ECX register.
The RDPMC instruction allows application code running at a privilege level of 1, 2, or 3 to read
the performance-monitoring counters if the PCE flag in the CR4 register is set. This instruction
is provided to allow performance monitoring by application code without incurring the overhead
of a call to an operating-system procedure.
The performance-monitoring counters are event counters that can be programmed to count
events such as the number of instructions decoded, number of interrupts received, or number of
cache loads. Appendix A, Performance-Monitoring Events, in the Intel Architecture Software
Developers Manual, Volume 3, lists all the events that can be counted.
The RDPMC instruction does not serialize instruction execution. That is, it does not imply that
all the events caused by the preceding instructions have been completed or that events caused
by subsequent instructions have not begun. If an exact event count is desired, software must use
a serializing instruction (such as the CPUID instruction) before and/or after the execution of the
RDPMC instruction.
The RDPMC instruction can execute in 16-bit addressing mode or virtual-8086 mode; however,
the full contents of the ECX register are used to determine the counter to access and a full 40-bit
result is returned (the low-order 32 bits in the EAX register and the high-order nine bits in the
EDX register).
Intel Architecture Compatibility
The RDPMC instruction was introduced into the Intel Architecture in the Pentium
®
Pro
processor and the Pentium
®
processor with MMX technology. The other Pentium
®
processors
have performance-monitoring counters, but they must be read with the RDMSR instruction.
Operation
IF (ECX = 0 OR 1) AND ((CR4.PCE = 1) OR ((CR4.PCE = 0) AND (CPL=0)))
THEN
EDX:EAX
<
PMC[ECX];
ELSE (* ECX is not 0 or 1 and/or CR4.PCE is 0 and CPL is 1, 2, or 3 *)
#GP(0); FI;
Opcode
Instruction
Description
0F 33
RDPMC
Read performance-monitoring counter specified by ECX
into EDX:EAX
