3-604
INSTRUCTION SET REFERENCE
RDTSCRead Time-Stamp Counter
Description
This instruction loads the current value of the processors time-stamp counter into the
EDX:EAX registers. The time-stamp counter is contained in a 64-bit MSR. The high-order 32
bits of the MSR are loaded into the EDX register, and the low-order 32 bits are loaded into the
EAX register. The processor increments the time-stamp counter MSR every clock cycle and
resets it to 0 whenever the processor is reset.
The time stamp disable (TSD) flag in register CR4 restricts the use of the RDTSC instruction.
When the TSD flag is clear, the RDTSC instruction can be executed at any privilege level; when
the flag is set, the instruction can only be executed at privilege level 0. The time-stamp counter
can also be read with the RDMSR instruction, when executing at privilege level 0.
The RDTSC instruction is not a serializing instruction. Thus, it does not necessarily wait until
all previous instructions have been executed before reading the counter. Similarly, subsequent
instructions may begin execution before the read operation is performed.
This instruction was introduced into the Intel Architecture in the Pentium
®
processor.
Operation
IF (CR4.TSD = 0) OR ((CR4.TSD = 1) AND (CPL=0))
THEN
EDX:EAX
<
TimeStampCounter;
ELSE (* CR4 is 1 and CPL is 1, 2, or 3 *)
#GP(0)
FI;
Flags Affected
None.
Protected Mode Exceptions
#GP(0)
If the TSD flag in register CR4 is set and the CPL is greater than 0.
Real-Address Mode Exceptions
#GP
If the TSD flag in register CR4 is set.
Virtual-8086 Mode Exceptions
#GP(0)
If the TSD flag in register CR4 is set.
Opcode
Instruction
Description
0F 31
RDTSC
Read time-stamp counter into EDX:EAX
