3-634
INSTRUCTION SET REFERENCE
SFENCE—Store Fence
Description
Weakly ordered memory types can enable higher performance through such techniques as out-
of-order issue, write-combining, and write-collapsing. Memory ordering issues can arise
between a producer and a consumer of data and there are a number of common usage models
which may be affected by weakly ordered stores:
1.library functions, which use weakly ordered memory to write results
2.compiler-generated code, which also benefit from writing weakly-ordered results
3.hand-written code
The degree to which a consumer of data knows that the data is weakly ordered can vary for these
cases. As a result, the SFENCE instruction provides a performance-efficient way of ensuring
ordering between routines that produce weakly-ordered results and routines that consume this
data. The SFENCE is ordered with respect to stores and other SFENCE instructions.
SFENCE uses the following ModRM encoding:
Mod (7:6) = 11B
Reg/Opcode (5:3) = 111B
R/M (2:0) = 000B
All other ModRM encodings are defined to be reserved, and use of these encodings risks incom-
patibility with future processors.
Operation
WHILE (NOT(preceding_stores_globally_visible)) WAIT();
Intel C/C++ Compiler Intrinsic Equivalent
void_mm_sfence(void)
Guarantees that every preceding store is globally visible before any subsequent store.
Numeric Exceptions
None.
OpcodeInstructionDescription
0F AE /7SFENCEGuarantees that every store instruction that precedes in program order the
store fence instruction is globally visible before any store instruction which
follows the fence is globally visible.
