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INSTRUCTION SET REFERENCE
SGDT/SIDTStore Global/Interrupt Descriptor Table Register
Description
These instructions store the contents of the global descriptor table register (GDTR) or the inter-
rupt descriptor table register (IDTR) in the destination operand. The destination operand speci-
fies a 6-byte memory location. If the operand-size attribute is 32 bits, the 16-bit limit field of the
register is stored in the lower two bytes of the memory location and the 32-bit base address is
stored in the upper four bytes. If the operand-size attribute is 16 bits, the limit is stored in the
lower two bytes and the 24-bit base address is stored in the third, fourth, and fifth byte, with the
sixth byte filled with 0s.
The SGDT and SIDT instructions are only useful in operating-system software; however, they
can be used in application programs without causing an exception to be generated.
Refer to LGDT/LIDTLoad Global/Interrupt Descriptor Table Register in this chapter for
information on loading the GDTR and IDTR.
Intel Architecture Compatibility
The 16-bit forms of the SGDT and SIDT instructions are compatible with the Intel 286
processor, if the upper eight bits are not referenced. The Intel 286 processor fills these bits with
1s; the Pentium
®
Pro, Pentium
®
, Intel486, and Intel386 processors fill these bits with 0s.
Opcode
Instruction
Description
0F 01 /0
SGDT m
Store GDTR to m
0F 01 /1
SIDT m
Store IDTR to m
