3-664
INSTRUCTION SET REFERENCE
STISet Interrupt Flag
Description
This instruction sets the interrupt flag (IF) in the EFLAGS register. After the IF flag is set, the
processor begins responding to external, maskable interrupts after the next instruction is
executed. The delayed effect of this instruction is provided to allow interrupts to be enabled just
before returning from a procedure (or subroutine). For instance, if an STI instruction is followed
by an RET instruction, the RET instruction is allowed to execute before external interrupts are
recognized
1
. This behavior allows external interrupts to be disabled at the beginning of a proce-
dure and enabled again at the end of the procedure. If the STI instruction is followed by a CLI
instruction (which clears the IF flag), the effect of the STI instruction is negated.
The IF flag and the STI and CLI instructions have no affect on the generation of exceptions and
NMI interrupts.
The following decision table indicates the action of the STI instruction (bottom of the table)
depending on the processors mode of operation and the CPL and IOPL of the currently running
program or procedure (top of the table).
NOTES:
XDont care.
NAction in Column 1 not taken.
YAction in Column 1 taken.
Opcode
Instruction
Description
FB
STI
Set interrupt flag; external, maskable interrupts enabled
at the end of the next instruction
1.Note that in a sequence of instructions that individually delay interrupts past the following instruction, only
the first instruction in the sequence is guaranteed to delay the interrupt, but subsequent interrupt-delaying
instructions may not delay the interrupt. Thus, in the following instruction sequence:
STI
MOV SS, AX
MOV ESP, EBP
interrupts may be recognized before MOV ESP, EBP executes, even though MOV SS, AX normally
delays interrupts for one instruction.
PE =
0
1
1
1
VM =
X
0
0
1
CPL
X
?
IOPL
> IOPL
=3
IOPL
X
X
X
=3
IF
<
1
Y
Y
N
Y
#GP(0)
N
N
Y
N
