3-714
INSTRUCTION SET REFERENCE
XCHGExchange Register/Memory with Register
Description
This instruction exchanges the contents of the destination (first) and source (second) operands.
The operands can be two general-purpose registers or a register and a memory location. If a
memory operand is referenced, the processors locking protocol is automatically implemented
for the duration of the exchange operation, regardless of the presence or absence of the LOCK
prefix or of the value of the IOPL. Refer to the LOCK prefix description in this chapter for more
information on the locking protocol.
This instruction is useful for implementing semaphores or similar data structures for process
synchronization. Refer to Section 7.1.2., Bus Locking in Chapter 7, Multiple-Processor
Management of the Intel Architecture Software Developers Manual, Volume 3, for more infor-
mation on bus locking.
The XCHG instruction can also be used instead of the BSWAP instruction for 16-bit operands.
Operation
TEMP
<
DEST
DEST
<
SRC
SRC
<
TEMP
Flags Affected
None.
Opcode
Instruction
Description
90+rw
XCHG AX,r16
Exchange r16 with AX
90+rw
XCHG r16,AX
Exchange AX with r16
90+rd
XCHG EAX,r32
Exchange r32 with EAX
90+rd
XCHG r32,EAX
Exchange EAX with r32
86 /r
XCHG r/m8,r8
Exchange r8 (byte register) with byte from r/m8
86 /r
XCHG r8,r/m8
Exchange byte from r/m8 with r8 (byte register)
87 /r
XCHG r/m16,r16
Exchange r16 with word from r/m16
87 /r
XCHG r16,r/m16
Exchange word from r/m16 with r16
87 /r
XCHG r/m32,r32
Exchange r32 with doubleword from r/m32
87 /r
XCHG r32,r/m32
Exchange doubleword from r/m32 with r32
