B-7
INSTRUCTION FORMATS AND ENCODINGS
AND Logical AND
register1 to register2
0010 000w : 11 reg1 reg2
register2 to register1
0010 001w : 11 reg1 reg2
memory to register
0010 001w : mod reg r/m
register to memory
0010 000w : mod reg r/m
immediate to register
immediate to AL, AX, or EAX
0010 010w : immediate data
immediate to memory
1000 00sw : mod 100 r/m : immediate data
ARPL Adjust RPL Field of Selector
from register
0110 0011 : 11 reg1 reg2
from memory
0110 0011 : mod reg r/m
BOUND Check Array Against Bounds
0110 0010 : mod reg r/m
BSF Bit Scan Forward
register1, register2
0000 1111 : 1011 1100 : 11 reg2 reg1
memory, register
0000 1111 : 1011 1100 : mod reg r/m
BSR Bit Scan Reverse
register1, register2
0000 1111 : 1011 1101 : 11 reg2 reg1
memory, register
0000 1111 : 1011 1101 : mod reg r/m
BSWAP Byte Swap
0000 1111 : 1100 1 reg
BT Bit Test
register, immediate
0000 1111 : 1011 1010 : 11 100 reg: imm8 data
memory, immediate
0000 1111 : 1011 1010 : mod 100 r/m : imm8 data
register1, register2
0000 1111 : 1010 0011 : 11 reg2 reg1
memory, reg
0000 1111 : 1010 0011 : mod reg r/m
BTC Bit Test and Complement
register, immediate
0000 1111 : 1011 1010 : 11 111 reg: imm8 data
memory, immediate
0000 1111 : 1011 1010 : mod 111 r/m : imm8 data
register1, register2
0000 1111 : 1011 1011 : 11 reg2 reg1
memory, reg
0000 1111 : 1011 1011 : mod reg r/m
BTR Bit Test and Reset
register, immediate
0000 1111 : 1011 1010 : 11 110 reg: imm8 data
memory, immediate
0000 1111 : 1011 1010 : mod 110 r/m : imm8 data
register1, register2
0000 1111 : 1011 0011 : 11 reg2 reg1
memory, reg
0000 1111 : 1011 0011 : mod reg r/m
Table B-10. Integer Instruction Formats and Encodings (Contd.)
Instruction and Format
Encoding
