B-13
INSTRUCTION FORMATS AND ENCODINGS
OR Logical Inclusive OR
register1 to register2
0000 100w : 11 reg1 reg2
register2 to register1
0000 101w : 11 reg1 reg2
memory to register
0000 101w : mod reg r/m
register to memory
0000 100w : mod reg r/m
immediate to register
1000 00sw : 11 001 reg : immediate data
immediate to AL, AX, or EAX
0000 110w : immediate data
immediate to memory
1000 00sw : mod 001 r/m : immediate data
OUT Output to Port
fixed port
1110 011w : port number
variable port
1110 111w
OUTS Output to DX Port
0110 111w
POP Pop a Word from the Stack
register
1000 1111 : 11 000 reg
register (alternate encoding)
0101 1 reg
memory
1000 1111 : mod 000 r/m
POP Pop a Segment Register from the Stack
segment register CS, DS, ES
000 sreg2 111
segment register SS
000 sreg2 111
segment register FS, GS
0000 1111: 10 sreg3 001
POPA/POPAD Pop All General Registers
0110 0001
POPF/POPFD Pop Stack into FLAGS or
EFLAGS Register
1001 1101
PUSH Push Operand onto the Stack
register
1111 1111 : 11 110 reg
register (alternate encoding)
0101 0 reg
memory
1111 1111 : mod 110 r/m
immediate
0110 10s0 : immediate data
PUSH Push Segment Register onto the Stack
segment register CS,DS,ES,SS
000 sreg2 110
segment register FS,GS
0000 1111: 10 sreg3 000
PUSHA/PUSHAD Push All General Registers0110 0000
PUSHF/PUSHFD Push Flags Register onto the
Stack
1001 1100
Table B-10. Integer Instruction Formats and Encodings (Contd.)
Instruction and Format
Encoding
