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TABLE OF CONTENTS
E.3.3.1.Exception Synchronization: What, Why and When. . . . . . . . . . . . . . . . . . . . E-14
E.3.3.2.Exception Synchronization Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-15
E.3.3.3.Proper Exception Synchronization in General . . . . . . . . . . . . . . . . . . . . . . . E-16
E.3.3.4.FPU Exception Handling Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-16
E.3.4.Need for Storing State of IGNNE# Circuit If Using FPU and SMM . . . . . . . . . . E-20
E.3.5.Considerations When FPU Shared Between Tasks . . . . . . . . . . . . . . . . . . . . . E-21
E.3.5.1.Speculatively Deferring FPU Saves, General Overview. . . . . . . . . . . . . . . . E-21
E.3.5.2.Tracking FPU Ownership . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-22
E.3.5.3.Interaction of FPU State Saves and Floating-point Exception Association. . E-22
E.3.5.4.Interrupt Routing From the Kernel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-25
E.3.5.5.Special Considerations for Operating Systems that Support
Streaming SIMD Extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-25
E.4.DIFFERENCES FOR HANDLERS USING NATIVE MODE. . . . . . . . . . . . . . . . . . E-26
E.4.1.Origin with the Intel 286 and Intel 287, and Intel386 and
Intel 387 Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-26
E.4.2.Changes with Intel486, Pentium®, and P6 Family Processors
with CR0.NE=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-27
E.4.3.Considerations When FPU Shared Between Tasks Using Native Mode. . . . . . E-27
APPENDIX F
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
F.1.TWO OPTIONS FOR HANDLING NUMERIC EXCEPTIONS . . . . . . . . . . . . . . . . . F-1
F.2.SOFTWARE EXCEPTION HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-1
F.3.EXCEPTION SYNCHRONIZATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-3
F.4.SIMD FLOATING-POINT EXCEPTIONS AND THE IEEE-754 STANDARD FOR
BINARY FLOATING-POINT COMPUTATIONS
F-4
F.4.1.Floating-Point Emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-4
F.4.2.Streaming SIMD Extensions Response To Floating-Point Exceptions . . . . . . . . F-6
F.4.2.1.Numeric Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-7
F.4.2.2.Results of Operations with NaN Operands or a NaN Result for
Streaming SIMD Extensions Numeric Instructions. . . . . . . . . . . . . . . . . . . . . F-7
F.4.2.3.Condition Codes, Exception Flags, and Response for Masked and
Unmasked Numeric Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-10
F.4.3.SIMD Floating-Point Emulation Implementation Example. . . . . . . . . . . . . . . . . F-13
