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Intel Volume 1: Basic Architecture

  1. Volume 1: Basic Architecture
  2. TABLE OF CONTENTS

  3. CHAPTER 1. ABOUT THIS MANUAL

  4. 1.1.OVERVIEW OF THE INTEL ARCHITECTURE SOFTWARE
  5. 1.4.NOTATIONAL CONVENTIONS
  6. 1.4.1.Bit and Byte Order

  7. CHAPTER 2. INTRODUCTION TO THE INTEL ARCHITECTURE

  8. 2.2.INCREASING INTEL ARCHITECTURE PERFORMANCE AND
  9. 2.5.DETAILED DESCRIPTION OF THE P6 FAMILY PROCESSOR
  10. 2.5.1.Memory Subsystem

  11. CHAPTER 3. BASIC EXECUTION ENVIRONMENT

  12. 3.1.MODES OF OPERATION
  13. 3.2.OVERVIEW OF THE BASIC EXECUTION ENVIRONMENT
  14. 3.3.MEMORY ORGANIZATION
  15. 3.4.MODES OF OPERATION
  16. 3.5.32-BIT VS. 16-BIT ADDRESS AND OPERAND SIZES
  17. 3.6.REGISTERS
  18. 3.6.2.Segment Registers
  19. 3.6.3.EFLAGS Register
  20. 3.6.3.1.STATUS FLAGS
  21. 3.6.3.2.DF FLAG
  22. 3.6.4.System Flags and IOPL Field
  23. 3.7.INSTRUCTION POINTER
  24. 3.8.OPERAND-SIZE AND ADDRESS-SIZE ATTRIBUTES

  25. CHAPTER 4. PROCEDURE CALLS, INTERRUPTS, AND EXCEPTIONS

  26. 4.1.PROCEDURE CALL TYPES
  27. 4.2.STACK
  28. 4.2.4.Procedure Linking Information
  29. 4.2.4.1.STACK-FRAME BASE POINTER
  30. 4.2.4.2.RETURN INSTRUCTION POINTER
  31. 4.3.3.Parameter Passing
  32. 4.3.3.1.PASSING PARAMETERS THROUGH THE GENERAL-PURPOSE
  33. 4.3.3.2.PASSING PARAMETERS ON THE STACK
  34. 4.3.3.3.PASSING PARAMETERS IN AN ARGUMENT LIST
  35. 4.3.4.Saving Procedure State Information
  36. 4.3.5.Calls to Other Privilege Levels
  37. 4.4.INTERRUPTS AND EXCEPTIONS
  38. 4.4.1.Call and Return Operation for Interrupt or Exception
  39. 4.5.PROCEDURE CALLS FOR BLOCK-STRUCTURED
  40. 4.5.1.ENTER Instruction
  41. 4.5.2.LEAVE Instruction

  42. CHAPTER 5. DATA TYPES AND ADDRESSING MODES

  43. 5.1.FUNDAMENTAL DATA TYPES
  44. 5.1.1.Alignment of Words, Doublewords, and Quadwords
  45. 5.2.NUMERIC, POINTER, BIT FIELD, AND STRING DATA TYPES
  46. 5.2.1.Integers
  47. 5.2.2.Unsigned Integers
  48. 5.2.3.BCD Integers
  49. 5.2.4.Pointers
  50. 5.2.5.Bit Fields
  51. 5.2.6.Strings
  52. 5.2.7.Floating-Point Data Types
  53. 5.2.8.MMX Technology Data Types
  54. 5.2.9.Streaming SIMD Extensions Data Types
  55. 5.3.OPERAND ADDRESSING
  56. 5.3.1.Immediate Operands
  57. 5.3.2.Register Operands
  58. 5.3.3.Memory Operands
  59. 5.3.3.1.SPECIFYING A SEGMENT SELECTOR
  60. 5.3.3.2.SPECIFYING AN OFFSET
  61. 5.3.3.3.ASSEMBLER AND COMPILER ADDRESSING MODES
  62. 5.3.4.I/O Port Addressing

  63. CHAPTER 6. INSTRUCTION SET SUMMARY

  64. 6.1.NEW INTEL ARCHITECTURE INSTRUCTIONS
  65. 6.1.1.New Instructions Introduced with the Streaming SIMD
  66. 6.1.2.New Instructions Introduced with the MMX Technology
  67. 6.1.3.New Instructions in the Pentium
  68. 6.1.4.New Instructions in the Pentium
  69. 6.1.5.New Instructions in the Intel486 Processor
  70. 6.2.INSTRUCTION SET LIST
  71. 6.2.1.Integer Instructions
  72. 6.2.1.1.DATA TRANSFER INSTRUCTIONS
  73. 6.2.1.2.BINARY ARITHMETIC INSTRUCTIONS
  74. 6.2.1.3.DECIMAL ARITHMETIC
  75. 6.2.1.4.LOGIC INSTRUCTIONS
  76. 6.2.1.5.SHIFT AND ROTATE INSTRUCTIONS
  77. 6.2.1.6.BIT AND BYTE INSTRUCTIONS
  78. 6.2.1.7.CONTROL TRANSFER INSTRUCTIONS
  79. 6.2.1.8.STRING INSTRUCTIONS
  80. 6.2.1.9.FLAG CONTROL INSTRUCTIONS
  81. 6.2.1.10.SEGMENT REGISTER INSTRUCTIONS
  82. 6.2.1.11.MISCELLANEOUS INSTRUCTIONS
  83. 6.2.2.MMX Technology Instructions
  84. 6.2.2.1.MMX DATA TRANSFER INSTRUCTIONS
  85. 6.2.2.2.MMX CONVERSION INSTRUCTIONS
  86. 6.2.2.3.MMX PACKED ARITHMETIC INSTRUCTIONS
  87. 6.2.2.4.MMX COMPARISON INSTRUCTIONS
  88. 6.2.2.5.MMX LOGIC INSTRUCTIONS
  89. 6.2.2.6.MMX SHIFT AND ROTATE INSTRUCTIONS
  90. 6.2.2.7.MMX STATE MANAGEMENT
  91. 6.2.3.Floating-Point Instructions
  92. 6.2.3.1.DATA TRANSFER
  93. 6.2.3.2.BASIC ARITHMETIC
  94. 6.2.3.3.COMPARISON
  95. 6.2.3.4.TRANSCENDENTAL
  96. 6.2.3.5.LOAD CONSTANTS
  97. 6.2.3.6.FPU CONTROL
  98. 6.2.4.System Instructions
  99. 6.2.5.1.STREAMING SIMD EXTENSIONS DATA TRANSFER INSTRUCTIONS
  100. 6.2.5.2.STREAMING SIMD EXTENSIONS CONVERSION INSTRUCTIONS
  101. 6.2.5.3.STREAMING SIMD EXTENSIONS PACKED ARITHMETIC
  102. 6.2.5.4.STREAMING SIMD EXTENSIONS COMPARISON INSTRUCTIONS
  103. 6.2.5.5.STREAMING SIMD EXTENSIONS LOGICAL INSTRUCTIONS
  104. 6.2.5.6.STREAMING SIMD EXTENSIONS DATA SHUFFLE INSTRUCTIONS
  105. 6.2.5.7.STREAMING SIMD EXTENSIONS ADDITIONAL SIMD-INTEGER
  106. 6.2.5.8.STREAMING SIMD EXTENSIONS CACHEABILITY CONTROL
  107. 6.2.5.9.STREAMING SIMD EXTENSIONS STATE MANAGEMENT
  108. 6.3.DATA MOVEMENT INSTRUCTIONS
  109. 6.3.1.General-Purpose Data Movement Instructions
  110. 6.3.1.1.MOVE INSTRUCTION
  111. 6.3.1.2.CONDITIONAL MOVE INSTRUCTIONS
  112. 6.3.1.3.EXCHANGE INSTRUCTIONS
  113. 6.3.2.Stack Manipulation Instructions
  114. 6.3.2.1.TYPE CONVERSION INSTRUCTIONS
  115. 6.3.2.2.SIMPLE CONVERSION
  116. 6.3.2.3.MOVE AND CONVERT
  117. Stack
  118. 6.4.BINARY ARITHMETIC INSTRUCTIONS
  119. 6.4.1.Addition and Subtraction Instructions
  120. 6.4.2.Increment and Decrement Instructions
  121. 6.4.3.Comparison and Sign Change Instruction
  122. 6.4.4.Multiplication and Divide Instructions
  123. 6.5.DECIMAL ARITHMETIC INSTRUCTIONS
  124. 6.5.1.Packed BCD Adjustment Instructions
  125. 6.5.2.Unpacked BCD Adjustment Instructions
  126. 6.6.LOGICAL INSTRUCTIONS
  127. 6.7.SHIFT AND ROTATE INSTRUCTIONS
  128. 6.7.1.Shift Instructions
  129. 6.7.2.Double-Shift Instructions
  130. 6.7.3.Rotate Instructions
  131. 6.8.BIT AND BYTE INSTRUCTIONS
  132. 6.8.1.Bit Test and Modify Instructions
  133. 6.8.2.Bit Scan Instructions
  134. 6.8.3.Byte Set on Condition Instructions
  135. 6.8.4.Test Instruction
  136. 6.9.CONTROL TRANSFER INSTRUCTIONS
  137. 6.9.1.Unconditional Transfer Instructions
  138. 6.9.1.1.JUMP INSTRUCTION
  139. 6.9.1.2.CALL AND RETURN INSTRUCTIONS
  140. 6.9.1.3.RETURN FROM INTERRUPT INSTRUCTION
  141. 6.9.2.1.CONDITIONAL JUMP INSTRUCTIONS
  142. 6.9.2.Conditional Transfer Instructions
  143. 6.9.2.2.LOOP INSTRUCTIONS
  144. 6.9.2.3.JUMP IF ZERO INSTRUCTIONS
  145. 6.9.3.Software Interrupts
  146. 6.10.STRING OPERATIONS
  147. 6.10.1.Repeating String Operations
  148. 6.11.I/O INSTRUCTIONS
  149. 6.12.ENTER AND LEAVE INSTRUCTIONS
  150. 6.13.1.Carry and Direction Flag Instructions
  151. 6.13.2.Interrupt Flag Instructions
  152. 6.13.3.EFLAGS Transfer Instructions
  153. 6.13.4.Interrupt Flag Instructions
  154. 6.14.SEGMENT REGISTER INSTRUCTIONS
  155. 6.14.1.Segment-Register Load and Store Instructions
  156. 6.14.2.Far Control Transfer Instructions
  157. 6.14.3.Software Interrupt Instructions
  158. 6.14.4.Load Far Pointer Instructions
  159. 6.15.MISCELLANEOUS INSTRUCTIONS
  160. 6.15.1.Address Computation Instruction
  161. 6.15.2.Table Lookup Instructions
  162. 6.15.3.Processor Identification Instruction
  163. 6.15.4.No-Operation and Undefined Instructions

  164. CHAPTER 7. FLOATING-POINT UNIT

  165. 7.1.COMPATIBILITY AND EASE OF USE OF THE INTEL
  166. 7.2.REAL NUMBERS AND FLOATING-POINT FORMATS
  167. 7.2.1.Real Number System
  168. 7.2.2.Floating-Point Format
  169. 7.2.2.1.NORMALIZED NUMBERS
  170. 7.2.2.2.BIASED EXPONENT
  171. 7.2.3.Real Number and Non-number Encodings
  172. 7.2.3.1.SIGNED ZEROS
  173. 7.2.3.2.NORMALIZED AND DENORMALIZED FINITE NUMBERS
  174. 7.2.3.3.SIGNED INFINITIES
  175. 7.2.3.4.NANS
  176. 7.2.4.Indefinite
  177. 7.3.FPU ARCHITECTURE
  178. 7.3.1.FPU Data Registers
  179. 7.3.1.1.PARAMETER PASSING WITH THE FPU REGISTER STACK
  180. 7.3.2.FPU Status Register
  181. 7.3.2.1.TOP OF STACK (TOP) POINTER
  182. 7.3.2.2.CONDITION CODE FLAGS
  183. 7.3.2.3.EXCEPTION FLAGS
  184. 7.3.2.4.STACK FAULT FLAG
  185. 7.3.3.Branching and Conditional Moves on FPU Condition
  186. 7.3.4.FPU Control Word
  187. 7.3.4.1.EXCEPTION-FLAG MASKS
  188. 7.3.4.2.PRECISION CONTROL FIELD
  189. 7.3.4.3.ROUNDING CONTROL FIELD
  190. 7.3.5.Infinity Control Flag
  191. 7.3.6.FPU Tag Word
  192. 7.3.7.FPU Instruction and Operand (Data) Pointers
  193. 7.3.8.Last Instruction Opcode
  194. 7.3.9.Saving the FPU's State
  195. 7.4.FLOATING-POINT DATA TYPES AND FORMATS
  196. 7.4.1.Real Numbers
  197. 7.4.2.Binary Integers
  198. 7.4.3.Decimal Integers
  199. 7.4.4.Unsupported Extended-Real Encodings
  200. 7.5.1.Escape (ESC) Instructions
  201. 7.5.2.FPU Instruction Operands
  202. 7.5.3.Data Transfer Instructions
  203. 7.5.4.Load Constant Instructions
  204. 7.5.5.Basic Arithmetic Instructions
  205. 7.5.6.Comparison and Classification Instructions
  206. 7.5.6.1.BRANCHING ON THE FPU CONDITION CODES
  207. 7.5.7.Trigonometric Instructions
  208. 7.5.8.Pi
  209. 7.5.9.Logarithmic, Exponential, and Scale
  210. 7.5.10.Transcendental Instruction Accuracy
  211. 7.5.11.FPU Control Instructions
  212. 7.5.12.Waiting Vs. Non-waiting Instructions
  213. 7.5.13.Unsupported FPU Instructions
  214. 7.6.OPERATING ON NANS
  215. 7.6.1.Operating on NaNs with Streaming SIMD Extensions
  216. 7.6.2.Uses for Signaling NANs
  217. 7.6.3.Uses for Quiet NANs
  218. 7.7.FLOATING-POINT EXCEPTION HANDLING
  219. 7.7.1.Arithmetic vs. Non-arithmetic Instructions
  220. 7.7.2.Automatic Exception Handling
  221. 7.7.3.Software Exception Handling
  222. 7.7.3.1.NATIVE MODE
  223. 7.7.3.2.MS-DOS* COMPATIBILITY MODE
  224. 7.7.3.3.TYPICAL FLOATING-POINT EXCEPTION HANDLER ACTIONS
  225. 7.8.FLOATING-POINT EXCEPTION CONDITIONS
  226. 7.8.1.Invalid Operation Exception
  227. 7.8.1.1.STACK OVERFLOW OR UNDERFLOW EXCEPTION (#IS)
  228. 7.8.1.2.INVALID ARITHMETIC OPERAND EXCEPTION (#IA)
  229. 7.8.2.Divide-By-Zero Exception (#Z)
  230. 7.8.3.Denormal Operand Exception (#D)
  231. 7.8.4.Numeric Overflow Exception (#O)
  232. 7.8.6.Inexact Result (Precision) Exception (#P)
  233. 7.8.7.Exception Priority
  234. 7.9.FLOATING-POINT EXCEPTION SYNCHRONIZATION

  235. CHAPTER 8. PROGRAMMING WITH THE INTEL MMX TECHNOLOGY

  236. 8.1.OVERVIEW OF THE MMX TECHNOLOGY PROGRAMMING
  237. 8.1.3.Single Instruction, Multiple Data (SIMD) Execution Model
  238. 8.1.4.Memory Data Formats
  239. 8.1.1.MMX Registers
  240. 8.1.2.MMX Data Types
  241. 8.1.5.Data Formats for MMX Registers
  242. 8.2.MMX INSTRUCTION SET
  243. 8.2.1.Saturation Arithmetic and Wraparound Mode
  244. 8.2.2.Instruction Operands
  245. 8.3.OVERVIEW OF THE MMX INSTRUCTION SET
  246. 8.3.1.Data Transfer Instructions
  247. 8.3.2.Arithmetic Instructions
  248. 8.3.3.Comparison Instructions
  249. 8.3.2.1.PACKED ADDITION AND SUBTRACTION
  250. 8.3.2.2.PACKED MULTIPLICATION
  251. 8.3.2.3.PACKED MULTIPLY ADD
  252. 8.3.4.Conversion Instructions
  253. 8.3.5.Logical Instructions
  254. 8.3.6.Shift Instructions
  255. 8.3.7.EMMS (Empty MMX State) Instruction
  256. 8.4.COMPATIBILITY WITH FPU ARCHITECTURE
  257. 8.4.1.MMX Instructions and the Floating-Point Tag Word
  258. 8.4.2.Effect of Instruction Prefixes on MMX Instructions
  259. 8.5.WRITING APPLICATIONS WITH MMX CODE
  260. 8.5.1.Detecting Support for MMX Technology Using the
  261. 8.5.2.Using the EMMS Instruction
  262. 8.5.3.Interfacing with MMX Code
  263. 8.5.4.Writing Code with MMX and Floating-Point Instructions
  264. 8.5.4.1.RECOMMENDATIONS AND GUIDELINES
  265. 8.5.5.Using MMX Code in a Multitasking Operating System
  266. 8.5.5.1.COOPERATIVE MULTITASKING OPERATING SYSTEM
  267. 8.5.5.2.PREEMPTIVE MULTITASKING OPERATING SYSTEM
  268. 8.5.6.Exception Handling in MMX Code
  269. 8.5.7.Register Mapping

  270. CHAPTER 9. PROGRAMMING WITH THE STREAMING SIMD EXTENSIONS

  271. 9.1.OVERVIEW OF THE STREAMING SIMD EXTENSIONS
  272. 9.1.1.SIMD Floating-Point Registers
  273. 9.1.2.SIMD Floating-Point Data Types
  274. 9.1.3.Single Instruction, Multiple Data (SIMD) Execution Model
  275. 9.1.4.Pentium
  276. 9.1.5.Memory Data Formats
  277. 9.1.6.SIMD Floating-Point Register Data Formats
  278. 9.1.7.SIMD Floating-Point Control/Status Register
  279. 9.1.8.Rounding Control Field
  280. 9.1.9.Flush-To-Zero
  281. 9.2.STREAMING SIMD EXTENSIONS SET
  282. 9.2.1.Instruction Operands
  283. 9.3.OVERVIEW OF THE STREAMING SIMD EXTENSIONS SET
  284. 9.3.1.Data Movement Instructions
  285. 9.3.2.Arithmetic Instructions
  286. 9.3.2.1.PACKED/SCALAR ADDITION AND SUBTRACTION
  287. 9.3.2.2.PACKED/SCALAR MULTIPLICATION AND DIVISION
  288. 9.3.2.3.PACKED/SCALAR SQUARE ROOT
  289. 9.3.2.4.PACKED MAXIMUM/MINIMUM
  290. 9.3.3.Comparison Instructions
  291. 9.3.4.Conversion Instructions
  292. 9.3.5.Logical Instructions
  293. 9.3.6.Additional SIMD Integer Instructions
  294. 9.3.7.Shuffle Instructions
  295. 9.3.8.State Management Instructions
  296. 9.3.9.Cacheability Control Instructions
  297. 9.4.COMPATIBILITY WITH FPU ARCHITECTURE
  298. 9.4.1.Effect of Instruction Prefixes on Streaming SIMD
  299. 9.5.WRITING APPLICATIONS WITH STREAMING SIMD
  300. 9.5.1.Detecting Support for Streaming SIMD Extensions Using
  301. 9.5.2.Interfacing with Streaming SIMD Extensions Procedures
  302. 9.5.3.Writing Code with MMX , Floating-Point, and Streaming
  303. 9.5.3.1.CACHEABILITY HINT INSTRUCTIONS
  304. 9.5.3.2.RECOMMENDATIONS AND GUIDELINES
  305. 9.5.4.Using Streaming SIMD Extensions Code in a Multitasking
  306. 9.5.4.1.COOPERATIVE MULTITASKING OPERATING SYSTEM
  307. 9.5.4.2.PREEMPTIVE MULTITASKING OPERATING SYSTEM
  308. 9.5.5.Exception Handling in Streaming SIMD Extensions

  309. CHAPTER 10. INPUT/OUTPUT

  310. 10.1.I/O PORT ADDRESSING
  311. 10.2.I/O PORT HARDWARE
  312. 10.3.I/O ADDRESS SPACE
  313. 10.3.1.Memory-Mapped I/O
  314. 10.4.I/O INSTRUCTIONS
  315. 10.5.PROTECTED-MODE I/O
  316. 10.5.1.I/O Privilege Level
  317. 10.5.2.I/O Permission Bit Map
  318. 10.6.ORDERING I/O

  319. CHAPTER 11. PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION

  320. 11.1.PROCESSOR IDENTIFICATION
  321. 11.3.CPUID INSTRUCTION EXTENSIONS
  322. 11.3.1.Version Information
  323. 11.3.2.Control Register Extensions

  324. APPENDIX A. EFLAGS CROSS-REFERENCE

  325. APPENDIX B. EFLAGS CONDITION CODES

  326. APPENDIX C. FLOATING-POINT EXCEPTIONS SUMMARY

  327. APPENDIX D. SIMD FLOATING-POINT EXCEPTIONS SUMMARY

  328. APPENDIX E. GUIDELINES FOR WRITING FPU EXCEPTIONS HANDLERS

  329. E.2.1.MS-DOS* Compatibility Mode in the Intel486 and
  330. E.2.1.1.BASIC RULES: WHEN FERR# IS GENERATED
  331. E.2.1.2.RECOMMENDED EXTERNAL HARDWARE TO SUPPORT THE
  332. E.2.1.3.NO-WAIT FPU INSTRUCTIONS CAN GET FPU INTERRUPT IN
  333. E.3.RECOMMENDED PROTOCOL FOR MS-DOS*
  334. E.3.1.Floating-Point Exceptions and Their Defaults
  335. E.3.2.Two Options for Handling Numeric Exceptions
  336. E.3.2.2.SOFTWARE EXCEPTION HANDLING
  337. E.3.3.Synchronization Required for Use of FPU Exception
  338. E.3.3.1.EXCEPTION SYNCHRONIZATION: WHAT, WHY AND WHEN
  339. E.3.3.2.EXCEPTION SYNCHRONIZATION EXAMPLES
  340. E.3.3.3.PROPER EXCEPTION SYNCHRONIZATION IN GENERAL
  341. E.3.3.4.FPU EXCEPTION HANDLING EXAMPLES
  342. E.3.5.1.SPECULATIVELY DEFERRING FPU SAVES, GENERAL OVERVIEW
  343. E.3.5.2.TRACKING FPU OWNERSHIP
  344. E.3.5.3.INTERACTION OF FPU STATE SAVES AND FLOATING-POINT
  345. E.3.5.4.INTERRUPT ROUTING FROM THE KERNEL
  346. E.3.5.5.SPECIAL CONSIDERATIONS FOR OPERATING SYSTEMS THAT
  347. E.4.DIFFERENCES FOR HANDLERS USING NATIVE MODE
  348. E.4.1.Origin with the Intel 286 and Intel 287, and Intel386 and
  349. E.4.2.Changes with Intel486 , Pentium
  350. E.4.3.Considerations When FPU Shared Between Tasks Using

  351. APPENDIX F. GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS

  352. F.1.TWO OPTIONS FOR HANDLING NUMERIC EXCEPTIONS
  353. F.2.SOFTWARE EXCEPTION HANDLING
  354. F.4.SIMD FLOATING-POINT EXCEPTIONS AND THE IEEE-754
  355. F.4.1.Floating-Point Emulation
  356. F.4.2.Streaming SIMD Extensions Response To Floating-Point
  357. Exceptions
  358. F.4.2.1.NUMERIC EXCEPTIONS
  359. F.4.2.2.RESULTS OF OPERATIONS WITH NAN OPERANDS OR A NAN
  360. F.4.2.3.CONDITION CODES, EXCEPTION FLAGS, AND RESPONSE FOR MASKED AND UNMASKED NUMERIC EXCEPTIONS
  361. F.4.3.SIMD Floating-Point Emulation Implementation Example

  362. INDEX A - B - C
  363. INDEX D - E
  364. INDEX F
  365. INDEX G - H - I
  366. INDEX J - L - M
  367. INDEX N - O - P
  368. INDEX Q - R
  369. INDEX S - T
  370. INDEX U - V - W - X - Z