7-54
FLOATING-POINT UNIT
7.8.3.Denormal Operand Exception (#D)
The FPU signals the denormal operand exception under the following conditions:
If an arithmetic instruction attempts to operate on a denormal operand (refer to Section
7.2.3.2., Normalized and Denormalized Finite Numbers).
If an attempt is made to load a denormal single- or double-real value into an FPU register.
(If the denormal value being loaded is an extended-real value, the denormal operand
exception is not reported.)
The flag (DE) for this exception is bit 1 of the FPU status word, and the mask bit (DM) is bit 1
of the FPU control word.
When a denormal operand exception occurs and the exception is masked, the FPU sets the DE
flag, then proceeds with the instruction. The denormal operand in single- or double-real format
is automatically normalized when converted to the extended-real format. Operating on denormal
numbers will produce results at least as good as, and often better than, what can be obtained
when denormal numbers are flushed to zero. In fact, subsequent operations will benefit from the
additional precision of the internal extended-real format. Most programmers mask this excep-
tion so that a computation may proceed, then analyze any loss of accuracy when the final result
is delivered.
When a denormal operand exception occurs and the exception is not masked, the DE flag is set
and a software exception handler is invoked (refer to Section 7.7.3., Software Exception
Handling). The top-of-stack pointer (TOP) and source operands remain unchanged. When
denormal operands have reduced significance due to loss of low-order bits, it may be advisable
to not operate on them. Precluding denormal operands from computations can be accomplished
by an exception handler that responds to unmasked denormal operand exceptions.
7.8.4.Numeric Overflow Exception (#O)
The FPU reports a floating-point numeric overflow exception (#O) whenever the rounded result
of an arithmetic instruction exceeds the largest allowable finite value that will fit into the real
format of the destination operand. For example, if the destination format is extended-real (80
bits), overflow occurs when the rounded result falls outside the unbiased range of
?
1.0
?
2
16384
to 1.0
?
2
16384
(exclusive). Numeric overflow can occur on arithmetic operations where the result
is stored in an FPU data register. It can also occur on store-real operations (with the FST and
Table 7-22. Divide-By-Zero Conditions and the Masked Responses to Them
Condition
Masked Response
Divide or reverse divide operation
with a 0 divisor.
Returns an
?
signed with the exclusive OR of the sign of the two
operands to the destination operand.
FYL2X instruction.
Returns an
?
signed with the opposite sign of the non-zero
operand to the destination operand.
FXTRACT instruction.
ST(1) is set to
?
; ST(0) is set to 0 with the same sign as the
source operand.
