9-7
PROGRAMMING WITH THE STREAMING SIMD EXTENSIONS
9.1.7.SIMD Floating-Point Control/Status Register
The control/status register is used to enable masked/unmasked numerical exception handling, to
set rounding modes, to set flush-to-zero mode, and to view status flags. The contents of this
register can be loaded with the LDMXCSR and FXRSTOR instructions and stored in memory
with the STMXCSR and FXSAVE instructions. Figure 9-4 shows the format and encoding of
the fields in the MXCSR.
Bits 5-0 indicate whether a SIMD floating-point numerical exception has been detected. They
are sticky flags, and can be cleared by using the LDMXCSR instruction to write zeroes to
these fields. If an LDMXCSR instruction clears a mask bit and sets the corresponding exception
flag bit, an exception will not be immediately generated. The exception will occur only upon the
next Streaming SIMD Extensions to cause this type of exception. Streaming SIMD Extensions
use only one exception flag for each exception. There is no provision for individual exception
reporting within a packed data type. In situations where multiple identical exceptions occur
within the same instruction, the associated exception flag is updated and indicates that at least
one of these conditions happened. These flags are cleared upon reset.
Bits 12-7 configure numerical exception masking; an exception type is masked if the corre-
sponding bit is set, and it is unmasked if the bit is clear. These enables are set upon reset,
meaning that all numerical exceptions are masked.
Bits 14-13 encode the rounding control, which provides for the common round to nearest mode,
as well as directed rounding and true chop (refer to Section 9.1.8., Rounding Control Field).
The rounding control is set to round to nearest upon reset.
Bit 15 (FZ) is used to turn on the Flush-To-Zero mode (refer to Section 9.1.9., Flush-To-Zero).
This bit is cleared upon reset, disabling the Flush-To-Zero mode.
The other bits of MXCSR (bits 31-16 and bit 6) are defined as reserved and cleared; attempting
to write a non-zero value to these bits, using either the FXRSTOR or LDMXCSR instructions,
will result in a general protection exception.
Figure 9-4. SIMD Floating-Point Control/Status Register Format
31-16
15
10
5
0
FRRPUOZ
Reserved
DIRPUOZDI
M
ZCCMMMMMs
v
d
EEEEEE
