INDEX
INDEX-6
Microarchitecture
detailed description. . . . . . . . . . . . . . . . . . . .2-9
overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
Micro-ops. . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-11
MM0, MM1, MM2, MM3, MM4, MM5, MM6,
MM7 registers . . . . . . . . . . . . . . . . . .8-2
MMX technology
arithmetic instructions. . . . . . . . . . . . . . . . . .8-9
comparison instructions . . . . . . . . . . . . . . . .8-9
compatibility with FPU architecture. . . . . . .8-11
conversion instructions. . . . . . . . . . . . . . . .8-10
CPUID instruction. . . . . . . . . . . . . . . . . . . .11-2
data transfer instructions . . . . . . . . . . . . . . .8-7
data types. . . . . . . . . . . . . . . . . . . . . . . . . . .8-3
detecting MMX technology with
CPUID instruction . . . . . . . . . . . . . . . . .8-11
detecting with CPUID instruction . . . . . . . .8-12
effect of instruction prefixes on
MMX instructions. . . . . . . . . . . . . . . . . .8-11
EMMS instruction . . . . . . . . . . . . . . . . . . . .8-10
exception handling in MMX code . . . . . . . .8-16
instruction operands. . . . . . . . . . . . . . . . . . .8-7
instruction set . . . . . . . . . . . . . . . . . . . .8-5
,
8-7
interfacing with MMX code . . . . . . . . . . . . .8-13
introduction to. . . . . . . . . . . . . . . . . . . . . . . .8-1
logical instructions . . . . . . . . . . . . . . . . . . .8-10
memory data formats . . . . . . . . . . . . . . . . . .8-4
mixing MMX and floating-point
instructions . . . . . . . . . . . . . . . . . . . . . .8-14
programming environment (overview) . . . . .8-1
register data formats. . . . . . . . . . . . . . . . . . .8-5
register mapping. . . . . . . . . . . . . . . . . . . . .8-16
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-2
saturation arithmetic. . . . . . . . . . . . . . . . . . .8-6
shift instructions . . . . . . . . . . . . . . . . . . . . .8-10
SIMD execution environment . . . . . . . . . . . .8-4
support for, determing. . . . . . . . . . . . . . . . .11-2
using MMX code in a multitasking
operating system environment . . . . . . .8-15
using the EMMS instruction . . . . . . . . . . . .8-12
wraparound mode. . . . . . . . . . . . . . . . . . . . .8-6
Modes, operating. . . . . . . . . . . . . . . . . . . . . . . .3-4
MOV instruction . . . . . . . . . . . . . . . . . . .6-20
,
6-43
MOVD instruction. . . . . . . . . . . . . . . . . . . . . . . .8-7
MOVQ instruction. . . . . . . . . . . . . . . . . . . . . . . .8-7
MOVS instruction. . . . . . . . . . . . . . . . . .3-13
,
6-40
MOVSX instruction. . . . . . . . . . . . . . . . . . . . . .6-26
MOVZX instruction. . . . . . . . . . . . . . . . . . . . . .6-26
MTRRs (memory type range registers)
presence of. . . . . . . . . . . . . . . . . . . . . . . . .11-2
MUL instruction . . . . . . . . . . . . . . . . . . . . . . . .6-27
N
NaN
description of . . . . . . . . . . . . . . . . . . . .7-5
,
7-8
encoding of. . . . . . . . . . . . . . . . . . . . .7-6
,
7-27
operating on . . . . . . . . . . . . . . . . . . . . . . . .7-43
SNaNs vs. QNaNs . . . . . . . . . . . . . . . . . . . 7-8
Near call
description of. . . . . . . . . . . . . . . . . . . . . . . . 4-5
operation. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Near pointer
description of. . . . . . . . . . . . . . . . . . . . . . . . 5-5
Near return
operation. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Near return operation. . . . . . . . . . . . . . . . . . . . 4-6
NEG instruction . . . . . . . . . . . . . . . . . . . . . . . 6-27
Non-arithmetic instructions, FPU . . . . . . . . . . 7-46
Non-number encodings, FPU. . . . . . . . . . . . . . 7-5
Non-waiting instructions. . . . . . . . . . . . .7-42
,
7-49
NOP instruction . . . . . . . . . . . . . . . . . . . . . . . 6-45
Normalized finite number . . . . . . . . . . . . . .7-4
,
7-6
NOT instruction. . . . . . . . . . . . . . . . . . . . . . . . 6-29
Notation
bit and byte order . . . . . . . . . . . . . . . . . . . . 1-5
exceptions. . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
hexadecimal and binary numbers. . . . . . . . 1-7
instruction operands . . . . . . . . . . . . . . . . . . 1-7
reserved bits . . . . . . . . . . . . . . . . . . . . . . . . 1-6
segmented addressing . . . . . . . . . . . . . . . . 1-7
Notational conventions. . . . . . . . . . . . . . . . . . . 1-5
NT (nested task) flag, EFLAGS register. . . . . 3-13
Numeric overflow exception (#O). . . . . .7-13
,
7-54
Numeric underflow exception (#U). . . . .7-13
,
7-56
O
OE (numeric overflow exception) flag,
FPU status word. . . . . . . . . . .7-14
,
7-55
OF (overflow) flag, EFLAGS register . . .3-12
,
4-17
Offset (operand addressing). . . . . . . . . . . . . . . 5-9
Operand
FPU instructions . . . . . . . . . . . . . . . . . . . . 7-32
instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Operand addressing, modes . . . . . . . . . . . . . . 5-6
Operand sizes . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Operand-size attribute
code segment . . . . . . . . . . . . . . . . . . . . . . 3-14
description of. . . . . . . . . . . . . . . . . . . . . . . 3-14
Operating modes . . . . . . . . . . . . . . . . . . . . . . . 3-4
OR instruction. . . . . . . . . . . . . . . . . . . . . . . . . 6-29
Ordering I/O . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6
OUT instruction. . . . . . . . . . . . . . .6-41
,
10-3
,
10-4
OUTS instruction . . . . . . . . . . . . .6-41
,
10-3
,
10-4
Overflow exception (#OF). . . . . . . . . . . . . . . . 4-17
Overflow, FPU exception
(see Numeric overflow exception)
Overflow, FPU stack. . . . . . . . . . . . . . . .7-51
,
7-52
P
P6 family processors
microarchitecture. . . . . . . . . . . . . . . . . .2-6
,
2-9
Packed BCD integers. . . . . . . . . . . . . . . . . . . . 5-5
