10-6
INPUT/OUTPUT
If in protected mode and the CPL is less than or equal to the current IOPL, the processor allows
all I/O operations to proceed. If the CPL is greater than the IOPL or if the processor is operating
in virtual-8086 mode, the processor checks the I/O permission bit map to determine if access to
a particular I/O port is allowed. Each bit in the map corresponds to an I/O port byte address. For
example, the control bit for I/O port address 29H in the I/O address space is found at bit position
1 of the sixth byte in the bit map. Before granting I/O access, the processor tests all the bits corre-
sponding to the I/O port being addressed. For a doubleword access, for example, the processors
tests the four bits corresponding to the four adjacent 8-bit port addresses. If any tested bit is set,
a general-protection exception (#GP) is signaled. If all tested bits are clear, the I/O operation is
allows to proceed.
Because I/O port addresses are not necessarily aligned to word and doubleword boundaries, the
processor reads two bytes from the I/O permission bit map for every access to an I/O port. To
prevent exceptions from being generated when the ports with the highest addresses are accessed,
an extra byte needs to included in the TSS immediately after the table. This byte must have all
of its bits set, and it must be within the segment limit.
It is not necessary for the I/O permission bit map to represent all the I/O addresses. I/O addresses
not spanned by the map are treated as if they had set bits in the map. For example, if the TSS
segment limit is 10 bytes past the bit-map base address, the map has 11 bytes and the first 80 I/O
ports are mapped. Higher addresses in the I/O address space generate exceptions.
If the I/O bit map base address is greater than or equal to the TSS segment limit, there is no I/O
permission map, and all I/O instructions generate exceptions when the CPL is greater than the
current IOPL. The I/O bit map base address must be less than or equal to DFFFH.
10.6.ORDERING I/O
When controlling I/O devices it is often important that memory and I/O operations be carried
out in precisely the order programmed. For example, a program may write a command to an I/O
port, then read the status of the I/O device from another I/O port. It is important that the status
returned be the status of the device after it receives the command, not before.
When using memory-mapped I/O, caution should be taken to avoid situations in which the
programmed order is not preserved by the processor. To optimize performance, the processor
allows cacheable memory reads to be reordered ahead of buffered writes in most situations.
Internally, processor reads (cache hits) can be reordered around buffered writes. When using
memory-mapped I/O, therefore, is possible that an I/O read might be performed before the
memory write of a previous instruction. The recommended method of enforcing program
ordering of memory-mapped I/O accesses with the Pentium
®
Pro, Pentium II, and Pentium
®
III
processors is to use the MTRRs to make the memory mapped I/O address space uncacheable;
for the Pentium and Intel486 processors, either the #KEN pin or the PCD flags can be used
for this purpose (refer to Section 10.3.1.). When the target of a read or write is in an uncacheable
region of memory, memory reordering does not occur externally at the processors pins (that is,
reads and writes appear in-order). Designating a memory mapped I/O region of the address
space as uncacheable insures that reads and writes of I/O devices are carried out in program
