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PROGRAMMING WITH THE STREAMING SIMD EXTENSIONS
done by checking the CPUID.FXSR bit; for a processor that does implement Streaming SIMD
Extensions, use the approach described in Section 9.5.1., Detecting Support for Streaming
SIMD Extensions Using the CPUID Instruction. For even more detailed information, refer to
the Intel Processor Identification and the CPUID Instruction Application Note (AP-485), order
number 241618-008 and Identifying Support for Streaming SIMD Extensions in the Processor
and Operating System (AP-900).
The operating systems can be classified into two types:
Cooperative multitasking operating systems
Preemptive multitasking operating systems
9.5.4.1.COOPERATIVE MULTITASKING OPERATING SYSTEM
This type of multitasking operating system does not save the FP and MMX state and SIMD
floating-point state when performing a context switch. Therefore, the application needs to save
the relevant state before relinquishing direct or indirect control to the operating system.
9.5.4.2.PREEMPTIVE MULTITASKING OPERATING SYSTEM
This type of multitasking operating system saves the FP and MMX state and SIMD floating-
point state when performing a context switch. Therefore, the application does not have to save
or restore SIMD floating-point state.
9.5.5.Exception Handling in Streaming SIMD Extensions
Streaming SIMD Extensions can generate two kinds of exceptions:
Non-numeric exceptions
Numeric exceptions
Streaming SIMD Extensions can generate the same type of memory access exceptions as the IA
instructions do. Some examples are: page fault, segment not present, and limit violations.
Existing exception handlers can handle these types of exceptions without any code modifica-
tion. The Streaming SIMD Extensions PREFETCH instruction hints will not generate any kind
of exception and instead will be ignored.
Streaming SIMD Extensions can generate the same six numeric exceptions that x87-FP instruc-
tions can generate. All SIMD floating-point numeric exceptions are reported independently of
x87-FP numeric exceptions. Independent masking and unmasking of SIMD floating-point
numeric exceptions is achieved by setting/resetting specific bits in the MXCSR register.
The application must ensure that the OS can support unmasked SIMD floating-point exceptions
before unmasking them. (Use the approach described in Section 9.5.1., Detecting Support for
Streaming SIMD Extensions Using the CPUID Instruction. For even more detailed informa-
tion, refer to the Intel Processor Identification and the CPUID Instruction Application Note
(AP-485), order number 241618-008 and Identifying Support for Streaming SIMD Extensions
