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PROGRAMMING WITH THE STREAMING SIMD EXTENSIONS
in the Processor and Operating System (AP-900).) If an application unmasks exceptions using
either FXRSTOR or LDMXCSR without the required OS support being enabled, an invalid
opcode fault, instead of a SIMD floating-point exception, will be generated on the first faulting
Streaming SIMD Extensions.
SIMD floating-point numeric exceptions are precise and occur as soon as the instruction
completes execution. They will not catch pending x87 floating-point exceptions and will not
cause assertion of FERR# (independent of the value of CR0.NE). In addition, they ignore the
assertion/de-assertion of IGNNE#.
For more details on SIMD floating-point exceptions and exception handlers, refer to Section
4.4., “Interrupts and Exceptions”, in Chapter 4, Procedure Calls, Interrupts, and Exceptions,
Appendix D, SIMD Floating-Point Exceptions Summary, and Appendix E, Guidelines for
Writing FPU Exceptions Handlers.
