7-49
FLOATING-POINT UNIT
Note that when exceptions are masked, the FPU may detect multiple exceptions in a single
instruction, because it continues executing the instruction after performing its masked response.
For example, the FPU can detect a denormalized operand, perform its masked response to this
exception, and then detect numeric underflow.
7.7.3.Software Exception Handling
The FPU in the Pentium
®
Pro, Pentium
®
, and Intel486 processors provides two different
modes of operation for invoking a software exception handler for floating-point exceptions:
native mode and MS-DOS compatibility mode. The mode of operation is selected with the NE
flag of control register CR0. (Refer to Chapter 2, System Architecture Overview, in the Intel
Architecture Software Developers Manual, Volume 3, for more information about the NE flag.)
7.7.3.1.NATIVE MODE
The native mode for handling floating-point exceptions is selected by setting the NE flag in
control register CR0 to 1. In this mode, if the FPU detects an exception condition while
executing a floating-point instruction and the exception is unmasked (the mask bit for the excep-
tion is cleared), the FPU sets the flag for the exception and the ES flag in the FPU status word.
It then invokes the software exception handler through the floating-point-error exception (#MF,
vector 16), immediately before execution of any of the following instructions in the processors
instruction stream:
The next floating-point instruction, unless it is one of the non-waiting instructions
(FNINIT, FNCLEX, FNSTSW, FNSTCW, FNSTENV, and FNSAVE).
The next WAIT/FWAIT instruction.
The next MMX instruction.
If the next floating-point instruction in the instruction stream is a non-waiting instruction, the
FPU executes the instruction without invoking the software exception handler.
7.7.3.2.MS-DOS* COMPATIBILITY MODE
If the NE flag in control register CR0 is set to 0, the MS-DOS compatibility mode for handling
floating-point exceptions is selected. In this mode, the software exception handler for floating-
point exceptions is invoked externally using the processors FERR#, INTR, and IGNNE# pins.
This method of reporting floating-point errors and invoking an exception handler is provided to
support the floating-point exception handling mechanism used in PC systems that are running
the MS-DOS or Windows* 95 operating system.
