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FLOATING-POINT UNIT
The MS-DOS compatibility mode is typically used as follows to invoke the floating-point
exception handler:
1.If the FPU detects an unmasked floating-point exception, it sets the flag for the exception
and the ES flag in the FPU status word.
2.If the IGNNE# pin is deasserted, the FPU then asserts the FERR# pin either immediately,
or else delayed (deferred) until just before the execution of the next waiting floating-point
instruction or MMX instruction. Whether the FERR# pin is asserted immediately or
delayed depends on the type of processor, the instruction, and the type of exception.
3.If a preceding floating-point instruction has set the exception flag for an unmasked FPU
exception, the processor freezes just before executing the next WAIT instruction, waiting
floating-point instruction, or MMX instruction. Whether the FERR# pin was asserted at
the preceding floating-point instruction or is just now being asserted, the freezing of the
processor assures that the FPU exception handler will be invoked before the new floating-
point (or MMX) instruction gets executed.
4.The FERR# pin is connected through external hardware to IRQ13 of a cascaded, program-
mable interrupt controller (PIC). When the FERR# pin is asserted, the PIC is programmed
to generate an interrupt 75H.
5.The PIC asserts the INTR pin on the processor to signal the interrupt 75H.
6.The BIOS for the PC system handles the interrupt 75H by branching to the interrupt 2
(NMI) interrupt handler.
7.The interrupt 2 handler determines if the interrupt is the result of an NMI interrupt or a
floating-point exception.
8.If a floating-point exception is detected, the interrupt 2 handler branches to the floating-
point exception handler.
If the IGNNE# pin is asserted, the processor ignores floating-point error conditions. This pin is
provided to inhibit floating-point exceptions from being generated while the floating-point
exception handler is servicing a previously signaled floating-point exception.
Appendix E, Guidelines for Writing FPU Exceptions Handlers, describes the MS-DOS compat-
ibility mode in much greater detail. This mode is somewhat more complicated in the Intel486
and Pentium
®
processor implementations, as described in Appendix E, Guidelines for Writing
FPU Exceptions Handlers.
7.7.3.3.TYPICAL FLOATING-POINT EXCEPTION HANDLER ACTIONS
After the floating-point exception handler is invoked, the processor handles the exception in the
same manner that it handles non-FPU exceptions. (The floating-point exception handler is
normally part of the operating system or executive software.) A typical action of the exception
handler is to store FPU state information in memory (with the FSTENV/FNSTENV or
FSAVE/FNSAVE instructions) so that it can evaluate the exception and formulate an appropriate
response (refer to Section 7.3.9., Saving the FPUs State).
