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PROGRAMMING WITH THE STREAMING SIMD EXTENSIONS
9.5.WRITING APPLICATIONS WITH STREAMING SIMD
EXTENSIONS CODE
The following sections give guidelines for writing applications code using the Streaming SIMD
Extensions.
9.5.1.Detecting Support for Streaming SIMD Extensions Using
the CPUID Instruction
Use the CPUID instruction to determine whether the processor supports the Streaming SIMD
Extensions set (refer to Section 3.2., Instruction Reference in Chapter 3, Instruction Set Refer-
ence of the Intel Architecture Software Developers Manual, Volume 2, for a detailed description
of the CPUID instruction). When support for the Streaming SIMD Extensions is detected by the
CPUID instruction, it is signaled by setting bit 25 (Streaming SIMD Extensions bit) in the
feature flags to 1. This only determines the Streaming SIMD Extensions are present. There are
other support considerations related to Streaming SIMD Extensions.
The Streaming SIMD Extensions extensions can be divided into four categories:
Single-precision, packed/scalar floating-point
Additional SIMD Integer Instructions
State management (i.e., FXSAVE/FXRSTOR)
Cacheability control, further subdivided as:
streaming stores for both packed FP (MOVNTPS) and integer MMX
(MASKMOVQ and MOVNTQ) instructions.
PREFETCH and SFENCE, which are not constrained to work with any specific
data type.
In order for an application to use SIMD floating-point extensions, the following conditions must
exist, otherwise an invalid opcode exception (Int 6) is generated:
CR0.EM(bit 2) = 0 (emulation disabled)
CR4.OSFXSR(bit 9) = 1 (OS supports saving SIMD floating-point state during context
switches)
CPUID.XMM(EDX bit 25) = 1 (processor supports Streaming SIMD Extensions)
To verify support for the additional SIMD Integer instructions, including the corresponding
cacheability control instructions, the application needs only to check that CPUID.XMM is set
to 1. The SIMD integer instructions behave otherwise identically to the original MMX
instructions; this implies that they will generate an invalid opcode exception if CR0.EM is set,
but will not generate an exception if CR4.OSFXSR is disabled/cleared.
To verify support for the PREFETCH and SFENCE instructions, the application needs only to
check that CPUID.XMM is set to 1; these instructions are not affected by CR0.EM or
CR4.OSFXSR.
