7-1
CHAPTER 7
FLOATING-POINT UNIT
The Intel Architecture (IA) Floating-Point Unit (FPU) provides high-performance floating-
point processing capabilities. It supports the real, integer, and BCD-integer data types and the
floating-point processing algorithms and exception handling architecture defined in the IEEE
754 and 854 Standards for Floating-Point Arithmetic. The FPU executes instructions from the
processors normal instruction stream and greatly improves the efficiency of IA processors in
handling the types of high-precision floating-point processing operations commonly found in
scientific, engineering, and business applications.
This chapter describes the data types that the FPU operates on, the FPUs execution environ-
ment, and the FPU-specific instruction set. Detailed descriptions of the FPU instructions are
given in Chapter 3, Instruction Set Reference, in the Intel Architecture Software Developers
Manual, Volume 2.
7.1.COMPATIBILITY AND EASE OF USE OF THE INTEL
ARCHITECTURE FPU
The architecture of the IA FPU has evolved in parallel with the architecture of early IA proces-
sors. The first Intel Math Coprocessors (the Intel 8087, Intel 287, and Intel 387) were companion
processors to the Intel 8086/8088, Intel 286, and Intel386 processors, respectively, and were
designed to improve and extend the numeric processing capability of the IA. The Intel486 DX
processor for the first time integrated the CPU and the FPU architectures on one chip. The
Pentium
®
processors FPU offered the same architecture as the Intel486 DX processors FPU,
but with improved performance. The Pentium
®
Pro processors FPU further extended the
floating-point processing capability of IA family of processors and added several new instruc-
tions to improve processing throughput.
Throughout this evolution, compatibility among the various generations of FPUs and math
coprocessors has been maintained. For example, the Pentium
®
Pro processors FPU is fully
compatible with the Pentium
®
and Intel486 DX processorss FPUs.
Each generation of the IA FPUs have been explicitly designed to deliver stable, accurate results
when programmed using straightforward pencil and paper algorithms, bringing the function-
ality and power of accurate numeric computation into the hands of the general user. The IEEE
754 standard specifically addresses this issue, recognizing the fundamental importance of
making numeric computations both easy and safe to use.
For example, some processors can overflow when two single-precision floating-point numbers
are multiplied together and then divided by a third, even if the final result is a perfectly valid 32-
bit number. The IA FPUs deliver the correctly rounded result. Other typical examples of unde-
sirable machine behavior in straightforward calculations occur when computing financial rate
of return, which involves the expression (1 + i)
n
or when solving for roots of a quadratic equa-
tion:
