7-15
FLOATING-POINT UNIT
flag is set, the FPU exception handler is invoked, using one of the techniques described in
Section 7.7.3., Software Exception Handling. (Note that if an exception flag is masked, the
FPU will still set the flag if its associated exception occurs, but it will not set the ES flag.)
The exception flags are sticky bits, meaning that once set, they remain set until explicitly
cleared. They can be cleared by executing the FCLEX/FNCLEX (clear exceptions) instructions,
by reinitializing the FPU with the FINIT/FNINIT or FSAVE/FNSAVE instructions, or by over-
writing the flags with an FRSTOR or FLDENV instruction.
The B-bit (bit 15) is included for 8087 compatibility only. It reflects the contents of the ES flag.
7.3.2.4.STACK FAULT FLAG
The stack fault flag (bit 6 of the FPU status word) indicates that stack overflow or stack under-
flow has occurred. The FPU explicitly sets the SF flag when it detects a stack overflow or under-
flow condition, but it does not explicitly clear the flag when it detects an invalid-arithmetic-
operand condition. When this flag is set, the condition code flag C1 indicates the nature of the
fault: overflow (C1 = 1) and underflow (C1 = 0). The SF flag is a sticky flag, meaning that
after it is set, the processor does not clear it until it is explicitly instructed to do so (for example,
by an FINIT/FNINIT, FCLEX/FNCLEX, or FSAVE/FNSAVE instruction).
Refer to Section 7.3.6., FPU Tag Word for more information on FPU stack faults.
7.3.3.Branching and Conditional Moves on FPU Condition
Codes
The IA FPU (beginning with the Pentium
®
Pro processor) supports two mechanisms for
branching and performing conditional moves according to comparisons of two floating-point
values. These mechanism are referred to here as the old mechanism and the new mecha-
nism.
The old mechanism is available in FPUs prior to the Pentium
®
Pro processor and in the
Pentium
®
Pro processor. This mechanism uses the floating-point compare instructions (FCOM,
FCOMP, FCOMPP, FTST, FUCOMPP, FICOM, and FICOMP) to compare two floating-point
values and set the condition code flags (C0 through C3) according to the results. The contents
of the condition code flags are then copied into the status flags of the EFLAGS register using a
two step process (refer to Figure 7-9):
1.The FSTSW AX instruction moves the FPU status word into the AX register.
2.The SAHF instruction copies the upper 8 bits of the AX register, which includes the
condition code flags, into the lower 8 bits of the EFLAGS register.
When the condition code flags have been loaded into the EFLAGS register, conditional jumps
or conditional moves can be performed based on the new settings of the status flags in the
EFLAGS register.
