7-16
FLOATING-POINT UNIT
The new mechanism is available only in the Pentium
®
Pro processor. Using this mechanism, the
new floating-point compare and set EFLAGS instructions (FCOMI, FCOMIP, FUCOMI, and
FUCOMIP) compare two floating-point values and set the ZF, PF, and CF flags in the EFLAGS
register directly. A single instruction thus replaces the three instructions required by the old
mechanism.
Note also that the FCMOVcc instructions (also new in the Pentium
®
Pro processor) allow condi-
tional moves of floating-point values (values in the FPU data registers) based on the setting of
the status flags (ZF, PF, and CF) in the EFLAGS register. These instructions eliminate the need
for an IF statement to perform conditional moves of floating-point values.
7.3.4.FPU Control Word
The 16-bit FPU control word (refer to Figure 7-10) controls the precision of the FPU and
rounding method used. It also contains the exception-flag mask bits. The control word is cached
in the FPU control register. The contents of this register can be loaded with the FLDCW instruc-
tion and stored in memory with the FSTCW/FNSTCW instructions.
When the FPU is initialized with either an FINIT/FNINIT or FSAVE/FNSAVE instruction, the
FPU control word is set to 037FH, which masks all floating-point exceptions, sets rounding to
nearest, and sets the FPU precision to 64 bits.
Figure 7-9. Moving the FPU Condition Codes to the EFLAGS Register
0
Condition
Code
Status
Flag
C0
C1
C2
C3
CF
(none)
PF
ZF
C
F
1
P
F
Z
F
7
31
EFLAGS Register
0
C
2
C
1
C
3
AX Register
0
C
15
0
C
2
C
1
C
3
FPU Status Word
0
C
15
FSTSW AX Instruction
SAHF Instruction
