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PROGRAMMING WITH THE STREAMING SIMD EXTENSIONS
point numbers, and sets the ZF, PF, and CF bits in the EFLAGS register as described above (the
OF, SF, and AF bits are cleared).
9.3.4.Conversion Instructions
These instructions support packed and scalar conversions between 128-bit SIMD floating-point
registers and either 64-bit integer MMX registers or 32-bit integer IA32 registers. The packed
versions behave identically to original MMX instructions, in the presence of x87-FP instruc-
tions, including:
Transition from x87-FP to MMX technology (TOS=0, FP valid bits set to all valid).
MMX instructions write ones (1s) to the exponent part of the corresponding x87-FP
register.
Use of EMMS for transition from MMX technology to x87-FP.
The CVTPI2PS (Convert packed 32-bit integer to packed, single-precision, floating-point)
instruction converts two 32-bit signed integers in an MMX register to the two least significant
single-precision, floating-point numbers. When the conversion is inexact, the rounded value
according to the rounding mode in MXCSR is returned. The upper two significant numbers in
the destination register are retained.
The CVTSI2SS (Convert scalar 32-bit integer to scalar single-precision, floating-point) instruc-
tion converts a 32-bit signed integer in an MMX register to the least significant single-preci-
sion, floating-point number. When the conversion is inexact, the rounded value according to the
rounding mode in MXCSR is returned. The upper three significant numbers in the destination
register are retained.
The CVTPS2PI (Convert packed, single-precision, floating-point to packed 32-bit integer)
instruction converts the two least significant single-precision, floating-point numbers to two 32-
bit signed integers in an MMX register. When the conversion is inexact, the rounded value
according to the rounding mode in MXCSR is returned. The CVTTPS2PI (Convert truncate
packed, single-precision, floating-point to packed 32-bit integer) instruction is similar to
CVTPS2PI, except if the conversion is inexact, in which case the truncated result is returned.
The CVTSS2SI (Convert scalar single-precision, floating-point to a 32-bit integer) instruction
converts the least significant single-precision, floating-point number to a 32-bit signed integer
in an IA 32-bit integer register. When the conversion is inexact, the rounded value according to
the rounding mode in MXCSR is returned. The CVTTSS2SI (Convert truncate scalar single-
precision, floating-point to scalar 32-bit integer) instruction is similar to CVTSS2SI, except if
the conversion is inexact, the truncated result is returned.
9.3.5.Logical Instructions
The ANDPS (Bit-wise packed logical AND for single-precision, floating-point) instruction
returns a bitwise AND between the two operands.
