E-26
GUIDELINES FOR WRITING FPU EXCEPTIONS HANDLERS
Software Developers Manual, Volume 2, for information about exceptions generated if the
memory region is not aligned).
3.Maintaining compatibility with legacy applications/libraries: The operating system
changes to support Streaming SIMD Extensions must be invisible to legacy applications or
libraries that deal only with floating-point instructions. The layout of the memory region
operated on by the FXSAVE/FXRSTOR instructions is different from the layout for the
FNSAVE/FRSTOR instructions. Specifically, the format of the FPU tag word and the
length of the various fields in the memory region is different. Care must be taken to return
the FPU state to a legacy application (e.g., when reporting FP exceptions) in the format it
expects.
4.Instruction semantic differences: There are some semantic differences between the way
the FXSAVE and FSAVE/FNSAVE instructions operate. The FSAVE/FNSAVE instruc-
tions clear the FPU after they save the state while the FXSAVE instruction saves the
FPU/Streaming SIMD Extensions state but does not clear it. Operating systems that use
FXSAVE to save the FPU state before making it available for another thread (e.g., during
thread switch time) should take precautions not to pass a dirty FPU to another appli-
cation.
E.4.DIFFERENCES FOR HANDLERS USING NATIVE MODE
The 8087 has a pin INT which it asserts when an unmasked exception occurs. But there is no
interrupt input pin in the 8086 or 8088 dedicated to its attachment, nor an interrupt vector num-
ber in the 8086 or 8088 specific for an FPU error assertion. But beginning with the Intel 286 and
Intel 287 hardware connections were dedicated to support the FPU exception, and interrupt vec-
tor 16 assigned to it.
E.4.1.Origin with the Intel 286 and Intel 287, and Intel386 and
Intel 387 Processors
The Intel 286 and Intel 287, and Intel386 and Intel 387 processor/coprocessor pairs are each
provided with ERROR# pins that are recommended to be connected between the processor and
FPU. If this is done, when an unmasked FPU exception occurs, the FPU records the exception,
and asserts its ERROR# pin. The processor recognizes this active condition of the ERROR# sta-
tus line immediately before execution of the next WAIT or FPU instruction (except for the no-
wait type) in its instruction stream, and branches to the routine at interrupt vector 16. Thus an
FPU exception will be handled before any other FPU instruction (after the one causing the error)
is executed (except for no-wait instructions, which will be executed without triggering the FPU
exception interrupt, but it will remain pending).
Using the dedicated interrupt 16 for FPU exception handling is referred to as the native mode.
It is the simplest approach, and the one recommended most highly by Intel.
