E-25
GUIDELINES FOR WRITING FPU EXCEPTIONS HANDLERS
be entered before the FNSAVE starts to execute, or it may be entered shortly after execution of
the FNSAVE. Since the FPU Owner is the kernel, the numeric exception handler simply exits,
discarding the exception. The DNA handler resumes execution, completing the FNSAVE of the
old floating-point context of thread A and the FRSTOR of the floating-point context for thread
B.
Thread A eventually gets an opportunity to handle the exception that was discarded during the
task switch. After some time, thread B is suspended, and thread A resumes execution. When
thread A starts to execute a floating-point instruction, once again the DNA exception handler is
entered. Bs FPU state is stored, and As FPU state is restored. Note that in restoring the FPU
state from As save area, the pending numeric exception flags are reloaded in to the floating-
point status word. Now when the DNA exception handler returns, thread A resumes execution
of the faulting floating-point instruction just long enough to immediately generate a numeric ex-
ception, which now gets handled in the normal way. The net result is that the task switch and
resulting FPU state swap via the DNA exception handler causes an extra numeric exception
which can be safely discarded.
E.3.5.4.INTERRUPT ROUTING FROM THE KERNEL
In MS-DOS, an application that wishes to handle numeric exceptions hooks interrupt 16 by plac-
ing its handler address in the interrupt vector table, and exiting via a jump to the previous inter-
rupt 16 handler. Protected mode systems that run MS-DOS programs under a subsystem can
emulate this exception delivery mechanism. For example, assume a protected mode O.S. that
runs with CR.NE = 1, and that runs MS-DOS programs in a virtual machine subsystem. The
MS-DOS program is set up in a virtual machine that provides a virtualized interrupt table. The
MS-DOS application hooks interrupt 16 in the virtual machine in the normal way. A numeric
exception will trap to the kernel via the real INT 16 residing in the kernel at ring 0. The INT 16
handler in the kernel then locates the correct MS-DOS virtual machine, and reflects the interrupt
to the virtual machine monitor. The virtual machine monitor then emulates an interrupt by jump-
ing through the address in the virtualized interrupt table, eventually reaching the applications
numeric exception handler.
E.3.5.5.SPECIAL CONSIDERATIONS FOR OPERATING SYSTEMS THAT
SUPPORT STREAMING SIMD EXTENSIONS
Operating systems that support Streaming SIMD Extensions instructions introduced with the
Pentium
®
III processor should use the FXSAVE and FXRSTOR instructions to save and restore
the new SIMD floating-point instruction register state as well as the floating-point state. Such
operating systems must consider the following issues:
1.Enlarged state save area: the FNSAVE/FRSTOR instructions operate on a 94-byte or
108-byte memory region, depending on whether they are executed in 16-bit or 32-bit
mode. The FXSAVE/FXRSTOR instructions operate on a 512-byte memory region.
2.Alignment requirements: the FXSAVE/FXRSTOR instructions require the memory
region on which they operate to be 16-byte aligned (refer to the individual instruction
instructions descriptions in Chapter 3, Instruction Set Reference, in the Intel Architecture
