E-22
GUIDELINES FOR WRITING FPU EXCEPTIONS HANDLERS
clear the TS bit before exit using the CLTS instruction. On return from the handler the faulting
thread will proceed with its floating-point computation.
Some operating systems save the FPU context on every task switch, typically because they also
change the linear address space between tasks. The problem and solution discussed in the fol-
lowing sections apply to these operating systems also.
E.3.5.2.TRACKING FPU OWNERSHIP
Since the contents of the FPU may not belong to the currently executing thread, the thread iden-
tifier for the last FPU user needs to be tracked separately. This is not complicated; the kernel
should simply provide a variable to store the thread identifier of the FPU owner, separate from
the variable that stores the identifier for the currently executing thread. This variable is updated
in the DNA exception handler, and is used by the DNA exception handler to find the FPU save
areas of the old and new threads. A simplified flow for a DNA exception handler is then:
1.Use the FPU Owner variable to find the FPU save area of the last thread to use the FPU.
2.Save the FPU contents to the old threads save area, typically using an FNSAVE or
FXSAVE instruction.
3.Set the FPU Owner variable to the identify the currently executing thread.
4.Reload the FPU contents from the new threads save area, typically using an FRSTOR or
FXRSTOR instruction.
5.Clear TS using the CLTS instruction and exit the DNA exception handler.
While this flow covers the basic requirements for speculatively deferred FPU state swaps, there
are some additional subtleties that need to be handled in a robust implementation.
E.3.5.3.INTERACTION OF FPU STATE SAVES AND FLOATING-POINT
EXCEPTION ASSOCIATION
Recall these key points from earlier in this document: When considering floating-point excep-
tions across all implementations of the IA, and across all floating-point instructions, an floating-
point exception can be initiated from any time during the excepting floating-point instruction,
up to just before the next floating-point instruction. The next floating-point instruction may
be the FNSAVE used to save the FPU state for a task switch. In the case of no-wait: instruc-
tions such as FNSAVE, the interrupt from a previously excepting instruction (NE=0 case) may
arrive just before the no-wait instruction, during, or shortly thereafter with a system dependent
delay. Note that this implies that an floating-point exception might be registered during the state
swap process itself, and the kernel and floating-point exception interrupt handler must be pre-
pared for this case.
NOTES
II Although CR0, bit 2, the emulation flag (EM), also causes a DNA exception, do not use the EM bit as a
surrogate for TS. EM means that no floating-point unit is available and that floating-point instructions
must be emulated. Using EM to trap on task switches is not compatible with IA MMX technology. If the
EM flag is set, MMX instructions raise the invalid opcode exception.
