5-7
DATA TYPES AND ADDRESSING MODES
5.3.2.Register Operands
Source and destination operands can be located in any of the following registers, depending on
the instruction being executed:
The 32-bit general-purpose registers (EAX, EBX, ECX, EDX, ESI, EDI, ESP, or EBP).
The 16-bit general-purpose registers (AX, BX, CX, DX, SI, DI, SP, or BP).
The 8-bit general-purpose registers (AH, BH, CH, DH, AL, BL, CL, or DL).
The segment registers (CS, DS, SS, ES, FS, and GS).
The EFLAGS register.
System registers, such as the global descriptor table (GDTR) or the interrupt descriptor
table register (IDTR).
Some instructions (such as the DIV and MUL instructions) use quadword operands contained
in a pair of 32-bit registers. Register pairs are represented with a colon separating them. For
example, in the register pair EDX:EAX, EDX contains the high order bits and EAX contains the
low order bits of a quadword operand.
Several instructions (such as the PUSHFD and POPFD instructions) are provided to load and
store the contents of the EFLAGS register or to set or clear individual flags in this register. Other
instructions (such as the Jcc instructions) use the state of the status flags in the EFLAGS register
as condition codes for branching or other decision making operations.
The processor contains a selection of system registers that are used to control memory manage-
ment, interrupt and exception handling, task management, processor management, and debug-
ging activities. Some of these system registers are accessible by an application program, the
operating system, or the executive through a set of system instructions. When accessing a
system register with a system instruction, the register is generally an implied operand of the
instruction.
5.3.3.Memory Operands
Source and destination operands in memory are referenced by means of a segment selector and
an offset (refer to Figure 5-5). The segment selector specifies the segment containing the
operand and the offset (the number of bytes from the beginning of the segment to the first byte
of the operand) specifies the linear or effective address of the operand.
Figure 5-5. Memory Operand Address
Offset (or Linear Address)
0
15
Segment
31
0
Selector
