9-19
PROGRAMMING WITH THE STREAMING SIMD EXTENSIONS
For more information on prefetch hints, refer to Section 9.5.3.1., Cacheability Hint Instruc-
tions. For even more detailed information, refer to Chapter 6, Optimizing Cache Utilization
for Pentium
®
III Processors, in the Intel Architecture Optimization Reference Manual (Order
Number 245127-001).
The SFENCE (Store Fence) instruction guarantees that every store instruction that precedes the
store fence instruction in program order is globally visible before any store instruction that
follows the fence. The SFENCE instruction provides an efficient way of ensuring ordering
between routines that produce weakly-ordered results and routines that consume this data.
The use of weakly-ordered memory types can be important under certain data sharing relation-
ships, such as a producer-consumer relationship. The use of weakly-ordered memory can make
the assembling of data more efficient, but care must be taken to ensure that the consumer obtains
the data that the producer intended it to see.
9.4.COMPATIBILITY WITH FPU ARCHITECTURE
The Streaming SIMD Extensions introduce a new state in the architecture. It is not aliased onto
the floating-point registers as are the MMX instructions. New instructions must be used to
save/restore the state of a Pentium
®
III processor.
The interface for context switching is discussed in detail in Section 11.5., Saving and Restoring
the Streaming SIMD Extensions state and Section 11.6., Designing Operating System Task
and Context Switching Facilities in Chapter 11, Streaming SIMD Extensions System Program-
ming, of the Intel Architecture Software Developers Manual, Volume 3.
9.4.1.Effect of Instruction Prefixes on Streaming SIMD
Extensions
The Streaming SIMD Extensions use prefixes as specified in Table 9-4, Table 9-5, and Table
9-6. The effect of multiple prefixes (more than one prefix from a group) is unpredictable and
may vary from processor to processor. Applying a prefix, in a manner not defined in this docu-
ment, is considered reserved behavior. For example, Table 9-4 shows general behavior for most
Streaming SIMD Extensions; however, the application of a prefix (Repeat, Repeat NE, Operand
Size) is reserved for the following instructions: ANDPS, ANDNPS, COMISS, FXRSTOR,
FXSAVE, ORPS, LDMXCSR, MOVAPS, MOVHPS, MOVLPS, MOVMSKPS, MOVNTPS,
MOVUPS, SHUFPS, STMXCSR, UCOMISS, UNPCKHPS, UNPCKLPS, XORPS.
