7-8
FLOATING-POINT UNIT
7.2.3.3.SIGNED INFINITIES
The two infinities, +
?
and
??
, represent the maximum positive and negative real numbers,
respectively, that can be represented in the floating-point format. Infinity is always represented
by a zero significand (fraction and integer bit) and the maximum biased exponent allowed in the
specified format (for example, 255
10
for the single-real format).
The signs of infinities are observed, and comparisons are possible. Infinities are always inter-
preted in the affine sense; that is,
?
is less than any finite number and +
?
is greater than any
finite number. Arithmetic on infinities is always exact. Exceptions are generated only when the
use of an infinity as a source operand constitutes an invalid operation.
Whereas denormalized numbers represent an underflow condition, the two infinity numbers
represent the result of an overflow condition. Here, the normalized result of a computation has
a biased exponent greater than the largest allowable exponent for the selected result format.
7.2.3.4.NANS
Since NaNs are non-numbers, they are not part of the real number line. In Figure 7-3, the
encoding space for NaNs in the FPU floating-point formats is shown above the ends of the real
number line. This space includes any value with the maximum allowable biased exponent and
a non-zero fraction. (The sign bit is ignored for NaNs.)
The IEEE standard defines two classes of NaN: quiet NaNs (QNaNs) and signaling NaNs
(SNaNs). A QNaN is a NaN with the most significant fraction bit set; an SNaN is a NaN with
the most significant fraction bit clear. QNaNs are allowed to propagate through most arithmetic
operations without signaling an exception. SNaNs generally signal an invalid operation excep-
tion whenever they appear as operands in arithmetic operations. Exceptions are discussed in
Section 7.7., Floating-Point Exception Handling.
Refer to Section 7.6., Operating on NaNs, for detailed information on how the FPU handles
NaNs.
7.2.4.Indefinite
For each FPU data type, one unique encoding is reserved for representing the special value
indefinite. For example, when operating on real values, the real indefinite value is a QNaN
(refer to Section 7.4.1., Real Numbers). The FPU produces indefinite values as responses
to masked floating-point exceptions.
7.3.FPU ARCHITECTURE
From an abstract, architectural view, the FPU is a coprocessor that operates in parallel with the
processors integer unit (refer to Figure 7-4). The FPU gets its instructions from the same
instruction decoder and sequencer as the integer unit and shares the system bus with the integer
unit. Other than these connections, the integer unit and FPU operate independently and in
parallel. (The actual microarchitecture of an IA processor varies among the various families of
processors. For example, the Pentium
®
Pro processor has two integer units and two FPUs;
