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CHAPTER 3
BASIC EXECUTION ENVIRONMENT
This chapter describes the basic execution environment of an Intel Architecture (IA) processor
as seen by assembly-language programmers. It describes how the processor executes instruc-
tions and how it stores and manipulates data. The parts of the execution environment described
here include memory (the address space), the general-purpose data registers, the segment regis-
ters, the EFLAGS register, and the instruction pointer register.
The execution environment for the floating-point unit (FPU) is described in Chapter 7, Floating-
Point Unit.
3.1.MODES OF OPERATION
The IA supports three operating modes: protected mode, real-address mode, and system
management mode. The operating mode determines which instructions and architectural
features are accessible:
Protected mode. The native state of the processor. In this mode all instructions and archi-
tectural features are available, providing the highest performance and capability. This is
the recommended mode for all new applications and operating systems.
Among the capabilities of protected mode is the ability to directly execute real-address
mode 8086 software in a protected, multitasking environment. This feature is called
virtual-8086 mode, although it is not actually a processor mode. Virtual-8086 mode is
actually a protected mode attribute that can be enabled for any task.
Real-address mode. Provides the programming environment of the Intel 8086 processor
with a few extensions (such as the ability to switch to protected or system management
mode). The processor is placed in real-address mode following power-up or a reset.
System management mode. A standard architectural feature unique to all Intel
processors, beginning with the Intel386 SL processor. This mode provides an operating
system or executive with a transparent mechanism for implementing platform-specific
functions such as power management and system security. The processor enters SMM
when the external SMM interrupt pin (SMI#) is activated or an SMI is received from the
advanced programmable interrupt controller (APIC). In SMM, the processor switches to a
separate address space while saving the entire context of the currently running program or
task. SMM-specific code may then be executed transparently. Upon returning from SMM,
the processor is placed back into its state prior to the system management interrupt.
The basic execution environment is the same for each of these operating modes, as is described
in the remaining sections of this chapter.
