E-3
GUIDELINES FOR WRITING FPU EXCEPTIONS HANDLERS
the same MS-DOS compatibility floating-point exception handling mechanism that was used in
the PC AT was used in PCs based on the Intel386.
E.2.IMPLEMENTATION OF THE MS-DOS* COMPATIBILITY MODE
IN THE INTEL486, PENTIUM
®
, AND P6 FAMILY
PROCESSORS
Beginning with the Intel486 processor, the IA provided a dedicated mechanism for enabling
the MS-DOS compatibility mode for FPU exceptions and for generating external FPU-excep-
tion signals while operating in this mode. The following sections describe the implementation
of the MS-DOS compatibility mode in Intel486, Pentium
®
processors, and P6 family proces-
sors. Also described is the recommended external hardware to support this mode of operation.
E.2.1.MS-DOS* Compatibility Mode in the Intel486 and
Pentium
®
Processors
In the Intel486, several things were done to enhance and speed up the numeric coprocessor,
now called the floating-point unit (FPU). The most important enhancement was that the FPU
was included in the same chip as the processor, for increased speed in FPU computations and
reduced latency for FPU exception handling. Also, for the first time, the MS-DOS compatibility
mode was built into the chip design, with the addition of the NE bit in control register CR0 and
the addition of the FERR# (Floating-point ERRor) and IGNNE# (IGNore Numeric Error) pins.
The NE bit selects the native FPU exception handling mode (NE = 1) or the MS-DOS compat-
ibility mode (NE = 0). When native mode is selected, all signaling of floating-point exceptions
is handled internally in the Intel486 chip, resulting in the generation of an interrupt 16.
When MS-DOS compatibility mode is selected the FERRR# and IGNNE# pins are used to sig-
nal floating-point exceptions. The FERR# output pin, which replaces the ERROR# pin from the
previous generations of IA numeric coprocessors, is connected to a PIC. A new input signal,
IGNNE#, is provided to allow the FPU exception handler to execute FPU instructions, if de-
sired, without first clearing the error condition and without triggering the interrupt a second
time. This IGNNE# feature is needed to replicate the capability that was provided on MS-DOS
compatible Intel 286 and Intel 287 and Intel386 and Intel 387 systems by turning off the
BUSY# signal, when inside the FPU exception handler, before clearing the error condition.
Note that Intel, in order to provide Intel486 processors for market segments which had no
need for an FPU, created the SX versions. These Intel486 SX processors did not contain the
floating-point unit. Intel also produced Intel 487 SX processors for end users who later decided
to upgrade to a system with an FPU. These Intel 487 SX processors are similar to standard
Intel486 processors with a working FPU on board. Thus, the external circuitry necessary to
support the MS-DOS compatibility mode for Intel 487 SX processors is the same as for standard
Intel486 DX processors.
The Pentium
®
and P6 family processors offer the same mechanism (the NE bit and the FERR#
and IGNNE# pins) as the Intel486 processors for generating FPU exceptions in MS-DOS
